Merge branch 'main' of github.com:openhwgroup/cvw

config/rv32gc/coverage.svh

@@ -25,3 +25,5 @@
 
 // Privileged extensions
 `include "ZicsrM_coverage.svh"
+`include "RV32VM_coverage.svh"
+`include "RV32VM_PMP_coverage.svh"

fpga/constraints/marked_debug.txt

@@ -5,3 +5,22 @@ wally/wallypipelinedcore.sv: logic                 InstrM
 lsu/lsu.sv: logic        IEUAdrM
 lsu/lsu.sv: logic       MemRWM
 mmu/hptw.sv: logic	   SATP_REGW
+uncore/spi_apb.sv: logic ShiftIn
+uncore/spi_apb.sv: logic  ReceiveShiftReg
+uncore/spi_apb.sv: logic  SCLKenable
+uncore/spi_apb.sv: logic  SampleEdge
+uncore/spi_apb.sv: logic  Active
+uncore/spi_apb.sv: statetype state
+uncore/spi_apb.sv: typedef rsrstatetype
+uncore/spi_apb.sv: logic SPICLK
+uncore/spi_apb.sv: logic SPIOut
+uncore/spi_apb.sv: logic SPICS
+uncore/spi_apb.sv: logic SckMode
+uncore/spi_apb.sv: logic SckDiv
+uncore/spi_apb.sv: logic ShiftEdge
+uncore/spi_apb.sv: logic TransmitShiftRegLoad
+uncore/spi_apb.sv: logic TransmitShiftReg
+uncore/spi_apb.sv: logic TransmitData
+uncore/spi_apb.sv: logic ReceiveData
+uncore/spi_apb.sv: logic ReceiveShiftRegEndian
+uncore/spi_apb.sv: logic ASR

fpga/constraints/small-debug-spi.xdc

@@ -191,7 +191,6 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
 connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadEmpty} ]]  
 
-
 # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
 #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
 connect_debug_port dbg_hub/clk [get_nets CPUCLK]

fpga/generator/Makefile

@@ -69,8 +69,8 @@ PreProcessFiles:
 	./insert_debug_comment.sh
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
 	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
 
 # build the Zero stage boot loader (ZSBL)
 .PHONY: zsbl

fpga/generator/wally.tcl

@@ -102,7 +102,8 @@ if {$board=="ArtyA7"} {
 } else {
     #source ../constraints/vcu-small-debug.xdc
     #source ../constraints/small-debug.xdc
-    source ../constraints/small-debug-spi.xdc
+    #source ../constraints/small-debug.xdc
+    source ../constraints/big-debug-spi.xdc
 }
 
 

sim/questa/wally.do

@@ -181,7 +181,7 @@ if {$DEBUG > 0} {
 # suppress spurious warnngs about
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
+set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
 set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
 vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
 

testbench/tests.vh

@@ -72,7 +72,8 @@ string coverage64gc[] = '{
   "pmpcfg2",
   "pmppriority",
   "pmpcbo",
-  "pmpadrdecs"
+  "pmpadrdecs",
+  "btbthrash"
 };
 
 string buildroot[] = '{

tests/coverage/btbthrash.S

@@ -0,0 +1,145 @@
+///////////////////////////////////////////
+// btbtrash.S
+//
+// Written: Rose Thompson rose@rosethompson.net 23 October 2024
+//
+// Purpose: Test the branch target buffer alias with divide and cache pipeline stalls
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+#include "WALLY-init-lib.h"
+
+main:
+
+    # Division test (having trouble with buildroot)
+        li x1, 1938759018
+        li x2, 3745029
+        li x3, 458
+        li x4, 29587209347
+        li x5, 28957
+        li x6, 298
+        li x7, 238562
+        li x8, 198674
+        li x9, 134
+        li x10, 906732
+        li x11, 29
+        li x12, 50912
+        li x13, 59
+        li x14, 6902385
+        li x15, 1923857
+        li x16, 3985
+        li x17, 3947
+        li x18, 15984
+        li x19, 5
+        li x20, 9684658489
+        li x21, 6548
+        li x22, 3564
+        li x23, 94
+        li x24, 689464
+        li x25, 42567
+        li x26, 98453
+        li x27, 648
+        li x28, 984
+        li x29, 6984
+        li x30, 864
+
+        # x31 will be our loop counter
+        li x31, 4
+
+.align 12
+jump1:  
+        divuw x0, x1, x2
+        j jump3
+jump4:
+        divuw x0, x5, x6
+        j jump5
+jump6:
+        divuw x0, x10, x9
+        j jump7
+jump8:
+        divuw x0, x14, x3
+        j jump9
+jump10:
+        divuw x0, x18, x17
+        j jump11
+jump12:
+        divuw x0, x21, x22
+        j jump13
+jump14:
+        divuw x0, x24, x25
+        j jump15
+jump16:
+        divuw x0, x29, x28
+        j jump17
+jump18:
+        divuw x0, x1, x30
+        j jump19
+jump20:
+        divuw x0, x3, x19
+        j jump21
+jump22:
+        divuw x0, x12, x13
+        j jump23
+
+.align 12 # size of the 1024 btb apart
+jump2:
+        j jump1
+jump3:  
+        divuw x0, x4, x3
+        j jump4
+jump5:  
+        divuw x0, x7, x8
+        j jump6
+jump7:  
+        divuw x0, x12, x11
+        j jump8
+jump9:  
+        divuw x0, x15, x16
+        j jump10
+jump11:  
+        divuw x0, x20, x19
+        j jump12
+jump13:  
+        divuw x0, x24, x23
+        j jump14
+jump15:  
+        divuw x0, x26, x27
+        j jump16
+jump17:  
+        divuw x0, x29, x30
+        j jump18
+jump19:  
+        divuw x0, x2, x3
+        j jump20
+jump21:  
+        divuw x0, x4, x5
+        j jump22
+jump23:  
+        divuw x0, x20, x21
+        #j jump22
+
+        fence.i
+
+        addi x31, x31, -1
+        bne x31, x0, jump1
+finsihed:       
+    j done
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S

@@ -553,7 +553,7 @@ test_cases:
 # Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
 
 SETUP_PLIC
-
+.4byte fmt, 0x00080000, write32_test        # reset format register
 .4byte delay1, 0x0000001, write32_test      # reset delay1 register
 .4byte cs_mode, 0x00000000, write32_test    # reset cs_mode
 .4byte tx_mark, 0x00000001, write32_test    # set transmit watermark to 1 (any entry turns mark off)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S

@@ -564,7 +564,7 @@ test_cases:
 # Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
 
 SETUP_PLIC
-
+.8byte fmt, 0x00080000, write32_test        # reset format register
 .8byte delay1, 0x0000001, write32_test      # reset delay1 register
 .8byte cs_mode, 0x00000000, write32_test    # reset cs_mode
 .8byte sck_div, 0x00000100, write32_test    # lower SPI clock rate so reads are done at correct time when ICACHE not supported