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https://github.com/openhwgroup/cvw
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Merge pull request #605 from davidharrishmc/dev
Fixed some lint errors in derived configs
This commit is contained in:
Rose Thompson
GitHub
commit
f5978b6e08
@ -59,10 +59,10 @@ BPRED_SIZE 32'd12
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# The syn configurations are trimmed down for faster synthesis.
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deriv syn_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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UNCORE_RAM_RANGE 32'h1FF
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DTIM_RANGE 64'h1FF
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IROM_RANGE 64'h1FF
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BOOTROM_RANGE 64'h1FF
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UNCORE_RAM_RANGE 64'h1FF
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WAYSIZEINBYTES 32'd512
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NUMWAYS 32'd1
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BPRED_SIZE 32'd5
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@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e
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# The syn_sram configurations use SRAM macros
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deriv syn_sram_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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DTIM_RANGE 64'h1FF
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IROM_RANGE 64'h1FF
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USE_SRAM 1
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# The other syn configurations have the same trimming
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@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
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# The following syn configurations gradually turn off features
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deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
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PMP_ENTRIES 0
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PMP_ENTRIES 32'd0
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deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
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PMP_ENTRIES 0
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PMP_ENTRIES 32'd0
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deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
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ZICSR_SUPPORTED 0
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@ -203,95 +203,95 @@ IDIV_ON_FPU 1
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# RAM latency and Burst mode for bus stress testing
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deriv ram_0_0_rv64gc rv64gc
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RAM_LATENCY 0
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RAM_LATENCY 32'd0
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BURST_EN 0
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deriv ram_1_0_rv64gc rv64gc
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RAM_LATENCY 1
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RAM_LATENCY 32'd1
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BURST_EN 0
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deriv ram_2_0_rv64gc rv64gc
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RAM_LATENCY 2
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RAM_LATENCY 32'd2
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BURST_EN 0
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deriv ram_1_1_rv64gc rv64gc
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RAM_LATENCY 1
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RAM_LATENCY 32'd1
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BURST_EN 1
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deriv ram_2_1_rv64gc rv64gc
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RAM_LATENCY 2
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RAM_LATENCY 32'd2
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BURST_EN 1
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# Branch predictor simulations
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deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc
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BPRED_SIZE 6
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BPRED_SIZE 32'd6
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deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
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BPRED_SIZE 8
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BPRED_SIZE 32'd8
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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BPRED_SIZE 10
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BPRED_SIZE 32'd10
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deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
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BPRED_SIZE 12
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BPRED_SIZE 32'd12
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deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
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BPRED_SIZE 14
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BPRED_SIZE 32'd14
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deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
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BPRED_SIZE 16
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BPRED_SIZE 32'd16
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deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 2
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RAS_SIZE 32'd2
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deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
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RAS_SIZE 3
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RAS_SIZE 32'd3
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deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
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RAS_SIZE 4
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RAS_SIZE 32'd4
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deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
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RAS_SIZE 6
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RAS_SIZE 32'd6
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 10
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RAS_SIZE 32'd10
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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RAS_SIZE 16
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RAS_SIZE 32'd16
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deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
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BTB_SIZE 6
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BTB_SIZE 32'd6
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deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
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BTB_SIZE 8
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BTB_SIZE 32'd8
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deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
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BTB_SIZE 12
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BTB_SIZE 32'd12
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deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
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BTB_SIZE 14
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BTB_SIZE 32'd14
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deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
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BTB_SIZE 16
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BTB_SIZE 32'd16
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deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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INSTR_CLASS_PRED 0
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@ -375,36 +375,36 @@ ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv32gc rv32gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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DCACHE_LINELENINBITS 32'd512
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ICACHE_NUMWAYS 32'd1
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ICACHE_WAYSIZEINBYTES 32'd4096
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ICACHE_LINELENINBITS 32'd512
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deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 1
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ICACHE_NUMWAYS 1
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DCACHE_NUMWAYS 32'd1
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ICACHE_NUMWAYS 32'd1
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deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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DCACHE_NUMWAYS 32'd4
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ICACHE_NUMWAYS 32'd4
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deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 8
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ICACHE_NUMWAYS 8
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DCACHE_NUMWAYS 32'd8
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ICACHE_NUMWAYS 32'd8
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deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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DCACHE_WAYSIZEINBYTES 32'd2048
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ICACHE_WAYSIZEINBYTES 32'd2048
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deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 256
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ICACHE_LINELENINBITS 256
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DCACHE_LINELENINBITS 32'd256
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ICACHE_LINELENINBITS 32'd256
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deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 1024
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ICACHE_LINELENINBITS 1024
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DCACHE_LINELENINBITS 32'd1024
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ICACHE_LINELENINBITS 32'd1024
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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@ -417,50 +417,54 @@ ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv64gc rv64gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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DCACHE_LINELENINBITS 32'd512
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ICACHE_NUMWAYS 32'd1
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ICACHE_WAYSIZEINBYTES 32'd4096
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ICACHE_LINELENINBITS 32'd512
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deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
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DCACHE_NUMWAYS 1
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ICACHE_NUMWAYS 1
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DCACHE_NUMWAYS 32'd1
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ICACHE_NUMWAYS 32'd1
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deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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DCACHE_NUMWAYS 32'd4
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ICACHE_NUMWAYS 32'd4
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deriv way_8_4096_512_rv64gc rv32gc way_1_4096_512_rv64gc
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DCACHE_NUMWAYS 32'd8
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ICACHE_NUMWAYS 32'd8
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deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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DCACHE_WAYSIZEINBYTES 32'd2048
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ICACHE_WAYSIZEINBYTES 32'd2048
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deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_LINELENINBITS 256
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ICACHE_LINELENINBITS 256
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DCACHE_LINELENINBITS 32'd256
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ICACHE_LINELENINBITS 32'd256
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deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_LINELENINBITS 1024
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ICACHE_LINELENINBITS 1024
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DCACHE_LINELENINBITS 32'd1024
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ICACHE_LINELENINBITS 32'd1024
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# TLB Size variants
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deriv tlb2_rv32gc rv32gc
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ITLB_ENTRIES 2
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DTLB_ENTRIES 2
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ITLB_ENTRIES 32'd2
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DTLB_ENTRIES 32'd2
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deriv tlb16_rv32gc rv32gc
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ITLB_ENTRIES 16
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DTLB_ENTRIES 16
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ITLB_ENTRIES 32'd16
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DTLB_ENTRIES 32'd16
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deriv tlb2_rv64gc rv64gc
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ITLB_ENTRIES 2
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DTLB_ENTRIES 2
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ITLB_ENTRIES 32'd2
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DTLB_ENTRIES 32'd2
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deriv tlb16_rv64gc rv64gc
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ITLB_ENTRIES 16
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DTLB_ENTRIES 16
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ITLB_ENTRIES 32'd16
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DTLB_ENTRIES 32'd16
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# Feature variants
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@ -102,6 +102,7 @@ localparam cvw_t P = '{
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BPRED_NUM_LHR : BPRED_NUM_LHR,
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BTB_SIZE : BTB_SIZE,
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RAS_SIZE : RAS_SIZE,
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INSTR_CLASS_PRED : INSTR_CLASS_PRED,
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RADIX : RADIX,
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DIVCOPIES : DIVCOPIES,
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ZBA_SUPPORTED : ZBA_SUPPORTED,
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@ -1,14 +1,26 @@
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#!/bin/bash
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# check for warnings in Verilog code
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# The verilator lint tool is faster and better than Questa so it is best to run this first.
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export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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basepath=$(dirname $0)/..
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for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do
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#for config in rv64gc; do
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if [ "$1" == "-nightly" ]; then
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
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derivconfigs=`ls $WALLY/config/deriv`
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for entry in $derivconfigs
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do
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configs[${#configs[@]}]=$entry
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done
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else
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
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fi
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for config in ${configs[@]}; do
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echo "$config linting..."
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if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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echo "Exiting after $config lint due to errors or warnings"
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exit 1
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fi
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@ -29,6 +29,7 @@ os.chdir(regressionDir)
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coverage = '-coverage' in sys.argv
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fp = '-fp' in sys.argv
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nightly = '-nightly' in sys.argv
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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# name: the name of this test configuration (used in printing human-readable
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@ -40,14 +41,20 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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# be any pattern grep accepts, see `man 1 grep` for more info).
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# edit this list to add more test cases
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configs = [
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TestCase(
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name="lints",
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variant="all",
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cmd="./lint-wally | tee {}",
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grepstr="All lints run with no errors or warnings"
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)
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]
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if (nightly):
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nightMode = "-nightly";
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configs = []
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else:
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nightMode = "";
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configs = [
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TestCase(
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name="lints",
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variant="all",
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cmd="./lint-wally " + nightMode + " | tee {}",
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grepstr="All lints run with no errors or warnings"
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)
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]
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def getBuildrootTC(boot):
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INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
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@ -78,7 +85,7 @@ for test in tests64i:
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configs.append(tc)
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tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
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tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
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tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zfad",
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#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
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for test in tests32gc:
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tc = TestCase(
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@ -126,15 +133,15 @@ for test in ahbTests:
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grepstr="All tests ran without failures")
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configs.append(tc)
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tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad",
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"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"]
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#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
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if (coverage): # delete all but 64gc tests when running coverage
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configs = []
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zicboz", "arch64zcb",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad"] # add when working: "arch64zcb", "arch64zicboz"
|
||||
if (fp):
|
||||
tests64gc.append("arch64f")
|
||||
tests64gc.append("arch64d")
|
||||
@ -150,7 +157,40 @@ for test in tests64gc:
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
# run derivative configurations if requested
|
||||
if (nightly):
|
||||
derivconfigtests = [
|
||||
["tlb2_rv32gc", ["wally32priv"]],
|
||||
["tlb16_rv32gc", ["wally32priv"]],
|
||||
["tlb2_rv64gc", ["wally64priv"]],
|
||||
["tlb16_rv64gc", ["wally64priv"]],
|
||||
["way_1_4096_512_rv64gc", ["arch64i", "arch64a"]],
|
||||
["way_2_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_8_4096_512_rv64gc", ["arch64i"]]
|
||||
]
|
||||
for test in derivconfigtests:
|
||||
config = test[0];
|
||||
tests = test[1];
|
||||
for t in tests:
|
||||
tc = TestCase(
|
||||
name=t,
|
||||
variant=config,
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do "+config+" "+t+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
tests32e = ["arch32e"]
|
||||
for test in tests32e:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32e",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
@ -59,7 +59,7 @@ if {$argc >= 3} {
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32imc rv32imc
|
||||
if {$2 eq "buildroot"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
if { $coverage } {
|
||||
echo "wally-batch buildroot coverage"
|
||||
@ -74,7 +74,7 @@ if {$2 eq "buildroot"} {
|
||||
run -all
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
@ -88,7 +88,7 @@ if {$2 eq "buildroot"} {
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "ahb"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
|
||||
@ -112,7 +112,7 @@ if {$2 eq "buildroot"} {
|
||||
# **** fix this so we can pass any number of +defines.
|
||||
# only allows 3 right now
|
||||
|
||||
vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
|
||||
vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt
|
||||
@ -126,7 +126,7 @@ if {$2 eq "buildroot"} {
|
||||
# power off -r /dut/core/*
|
||||
|
||||
} else {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
if {$coverage} {
|
||||
|
||||
2
src/cache/cacheLRU.sv
vendored
2
src/cache/cacheLRU.sv
vendored
@ -143,7 +143,7 @@ module cacheLRU
|
||||
// This is a two port memory.
|
||||
// Every cycle must read from CacheSetData and each load/store must write the new LRU.
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
|
||||
if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0;
|
||||
if(CacheEn) begin
|
||||
if(ClearValid & ~FlushStage)
|
||||
LRUMemory[PAdr] <= '0;
|
||||
|
||||
@ -162,6 +162,7 @@ typedef struct packed {
|
||||
int BPRED_SIZE;
|
||||
int BTB_SIZE;
|
||||
int RAS_SIZE;
|
||||
logic INSTR_CLASS_PRED; // is class predictor enabled
|
||||
|
||||
// FPU division architecture
|
||||
int RADIX;
|
||||
|
||||
@ -270,9 +270,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
// floating-point load immediate: fli
|
||||
if (P.ZFA_SUPPORTED) begin
|
||||
logic [4:0] Rs1E;
|
||||
logic [1:0] Fmt2E; // Two-bit format field from instruction
|
||||
|
||||
flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
|
||||
fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE));
|
||||
flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
|
||||
fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE));
|
||||
end else assign FliResE = '0;
|
||||
|
||||
// fmv.*.x: NaN Box SrcA to extend integer to requested FP size
|
||||
@ -287,7 +289,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
FmtE, PreIntSrcE); // NaN boxing zeroes
|
||||
end
|
||||
// fmvp.*.x: Select pair of registers
|
||||
if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED))
|
||||
if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN))
|
||||
assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x
|
||||
else assign IntSrcE = PreIntSrcE;
|
||||
|
||||
@ -311,11 +313,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
|
||||
// sign extend to XLEN if necessary
|
||||
if (P.FLEN>P.XLEN)
|
||||
if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
|
||||
else assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
|
||||
if (P.FLEN >= 2*P.XLEN)
|
||||
if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
|
||||
else assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
|
||||
else
|
||||
assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
|
||||
assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE};
|
||||
mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
|
||||
|
||||
// E/M pipe registers
|
||||
|
||||
@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
|
||||
endcase
|
||||
end
|
||||
|
||||
assign CycleFlag = Cycle == P.RAM_LATENCY;
|
||||
assign CycleFlag = Cycle == P.RAM_LATENCY[7:0];
|
||||
assign CntEn = NextState == DELAY;
|
||||
assign DelayReady = NextState == DELAY;
|
||||
assign CntRst = NextState == READY;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user