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Fixed linting issues.

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This commit is contained in:
Ross Thompson 2022-04-01 15:20:45 -05:00
parent 178ecaa451
commit f58a1eff9e
2 changed files with 3 additions and 3 deletions
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2
pipelined/src/generic/flop/bram2p1r1w.sv
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@ -78,8 +78,8 @@ module bram2p1r1w
end end
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
initial begin
if(PRELOAD_ENABLED) begin if(PRELOAD_ENABLED) begin
initial begin
RAM[0] = 64'h94e1819300002197; RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081; RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301; RAM[2] = 64'h4481440143814301;

2
pipelined/src/uncore/uartPC16550D.sv
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@ -310,7 +310,7 @@ module uartPC16550D(
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
end else begin end else begin
rxdataready <= #1 0; rxdataready <= #1 0;
RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
end end
end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register
if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents