diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/flop/bram2p1r1w.sv
index 58038b8cc..485df2aa4 100644
--- a/pipelined/src/generic/flop/bram2p1r1w.sv
+++ b/pipelined/src/generic/flop/bram2p1r1w.sv
@@ -78,8 +78,8 @@ module bram2p1r1w
   end
  -----/\----- EXCLUDED -----/\----- */
 
-  initial begin
-	if(PRELOAD_ENABLED) begin
+  if(PRELOAD_ENABLED) begin
+    initial begin
       RAM[0] =  64'h94e1819300002197; 
       RAM[1] =  64'h4281420141014081; 
       RAM[2] =  64'h4481440143814301; 
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index 267e38fd4..e2fd7b1c9 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -310,7 +310,7 @@ module uartPC16550D(
           if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
         end else begin
           rxdataready <= #1 0;
-          RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
+          RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
         end
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register
         if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents