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Merge branch 'fix'

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This commit is contained in:
Rose Thompson 2023-12-20 13:10:30 -06:00
commit f52ad13a65
2 changed files with 6 additions and 4 deletions
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2
src/generic/mem/ram1p1rwbe.sv
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@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
output logic [WIDTH-1:0] dout output logic [WIDTH-1:0] dout
); );
bit [WIDTH-1:0] RAM[DEPTH-1:0]; logic [WIDTH-1:0] RAM[DEPTH-1:0];
// *************************************************************************** // ***************************************************************************
// TRUE SRAM macro // TRUE SRAM macro

6
src/mmu/hptw.sv
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@ -102,6 +102,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay; logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
logic HPTWAccessFaultDelay; logic HPTWAccessFaultDelay;
logic TakeHPTWFault, TakeHPTWFaultDelay; logic TakeHPTWFault, TakeHPTWFaultDelay;
logic [P.XLEN-1:0] ReadDataNoXM;
// map hptw access faults onto either the original LSU load/store fault or instruction access fault // map hptw access faults onto either the original LSU load/store fault or instruction access fault
assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
@ -154,7 +155,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] AccessedPTE; logic [P.XLEN-1:0] AccessedPTE;
assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0 assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation.
mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
assign SaveHPTWAdr = WalkerState == L0_ADR; assign SaveHPTWAdr = WalkerState == L0_ADR;
@ -190,7 +192,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
end else begin // block: hptwwrites end else begin // block: hptwwrites
assign NextPTE = ReadDataM; assign NextPTE = ReadDataNoXM;
assign HPTWAdr = HPTWReadAdr; assign HPTWAdr = HPTWReadAdr;
assign HPTWUpdateDA = '0; assign HPTWUpdateDA = '0;
assign UpdatePTE = '0; assign UpdatePTE = '0;