From 18a96740d5686bfbe0330f0c9858754a4931eecd Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 20 Dec 2023 13:10:20 -0600
Subject: [PATCH] Revert RAM logic to bit change. Added logic to hptw to
 prevent x propagation.

---
 src/generic/mem/ram1p1rwbe.sv | 2 +-
 src/mmu/hptw.sv               | 8 +++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 95572228a..4af3c255c 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
   output logic [WIDTH-1:0]        dout
 );
 
-  bit [WIDTH-1:0]               RAM[DEPTH-1:0];
+  logic [WIDTH-1:0]               RAM[DEPTH-1:0];
 
   // ***************************************************************************
   // TRUE SRAM macro
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index ab5e571c8..80e4fc9f0 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -102,7 +102,8 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   logic                     HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
   logic                     HPTWAccessFaultDelay;
   logic                     TakeHPTWFault, TakeHPTWFaultDelay;
-
+  logic [P.XLEN-1:0]        ReadDataNoXM;
+  
   // map hptw access faults onto either the original LSU load/store fault or instruction access fault
   assign LSUAccessFaultM         = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
   assign HPTWLoadAccessFault     = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
@@ -154,7 +155,8 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0]    AccessedPTE;
 
     assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
+    assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation.
+    mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
     flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
     
     assign SaveHPTWAdr = WalkerState == L0_ADR;
@@ -190,7 +192,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;  // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
 
   end else begin // block: hptwwrites
-    assign NextPTE = ReadDataM;
+    assign NextPTE = ReadDataNoXM;
     assign HPTWAdr = HPTWReadAdr;
     assign HPTWUpdateDA = '0;
     assign UpdatePTE = '0;