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fdivsqrtfsm cleanup
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@ -62,29 +62,27 @@ module fdivsqrtfsm(
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statetype state;
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logic [`DURLEN-1:0] step;
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logic WZero;
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//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
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logic [`DIVb+3:0] W;
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logic SpecialCase;
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logic WZero;
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logic [`DIVb+3:0] W;
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// check for early termination on an exact result. If the result is not exact, the sticky should be set
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if (`RADIX == 2) begin
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logic [`DIVb+3:0] FZeroD, FSticky;
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logic [`DIVb+2:0] LastK, FirstK;
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assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
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logic [`DIVb+3:0] FZero;
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logic [`DIVb+2:0] FirstK;
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assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
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assign FZeroD = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
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assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
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// *** |... for continual -1 is not efficent fix - also only needed for radix-2
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assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZeroD)==0)&qn[`DIVCOPIES-1]);
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assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
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assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZero)==0)&qn[`DIVCOPIES-1]);
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end else begin
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assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
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end
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assign DivSE = ~WZero;
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// Determine if sticky bit is negative
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assign W = WC+WS;
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assign NegSticky = W[`DIVb+3];
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assign EarlyTermShiftE = step;
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// terminate immediately on special cases
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