diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 0630ed0c4..05f48f70e 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -62,29 +62,27 @@ module fdivsqrtfsm(
   statetype state;
 
   logic [`DURLEN-1:0] step;
-  logic WZero;
-  //logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
-  logic [`DIVb+3:0] W;
   logic SpecialCase;
- 
+  
+  logic WZero;
+  logic [`DIVb+3:0] W;
+
   // check for early termination on an exact result.  If the result is not exact, the sticky should be set
   if (`RADIX == 2) begin
-    logic [`DIVb+3:0] FZeroD, FSticky;
-    logic [`DIVb+2:0] LastK, FirstK;
-    assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
+    logic [`DIVb+3:0] FZero;
+    logic [`DIVb+2:0] FirstK;
     assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
-    assign FZeroD = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
-    assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
-    // *** |... for continual -1 is not efficent fix - also only needed for radix-2
-    assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZeroD)==0)&qn[`DIVCOPIES-1]);
+    assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
+    assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZero)==0)&qn[`DIVCOPIES-1]);
   end else begin
     assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
   end 
   assign DivSE = ~WZero;
 
-
+  // Determine if sticky bit is negative
   assign W = WC+WS;
   assign NegSticky = W[`DIVb+3];
+
   assign EarlyTermShiftE = step;
 
   // terminate immediately on special cases