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Formatted subword* and bytemask.

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This commit is contained in:
Ross Thompson 2023-01-18 18:20:22 -06:00
parent f288b9ca14
commit f34c67722d
3 changed files with 15 additions and 6 deletions
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7
pipelined/src/lsu/subwordread.sv
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/////////////////////////////////////////// ///////////////////////////////////////////
// subwordread.sv // subwordread.sv
// //
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu
// Modified: // Created: 9 January 2021
// Modified: 18 January 2023
// //
// Purpose: Extract subwords and sign extend for reads // Purpose: Extract subwords and sign extend for reads
// //
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

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pipelined/src/lsu/subwordwrite.sv
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@ -1,11 +1,14 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subwordwrite.sv // subwordwrite.sv
// //
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu
// Modified: // Created: 9 January 2021
// Modified: 18 January 2023
// //
// Purpose: Masking and muxing for subword writes // Purpose: Masking and muxing for subword writes
// //
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

7
pipelined/src/lsu/swbytemask.sv
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@ -1,11 +1,14 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// swbytemask.sv // swbytemask.sv
// //
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu
// Modified: // Created: 9 January 2021
// Modified: 18 January 2023
// //
// Purpose: On-chip RAM, external to core // Purpose: On-chip RAM, external to core
// //
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University