From f34c67722db5977e2b819b83927992ee9284807e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 18 Jan 2023 18:20:22 -0600 Subject: [PATCH] Formatted subword* and bytemask. --- pipelined/src/lsu/subwordread.sv | 7 +++++-- pipelined/src/lsu/subwordwrite.sv | 7 +++++-- pipelined/src/lsu/swbytemask.sv | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index ade4d3d43..784db694d 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -1,11 +1,14 @@ /////////////////////////////////////////// // subwordread.sv // -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Written: David_Harris@hmc.edu +// Created: 9 January 2021 +// Modified: 18 January 2023 // // Purpose: Extract subwords and sign extend for reads // +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index ae18b8402..ee26b78fd 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -1,11 +1,14 @@ /////////////////////////////////////////// // subwordwrite.sv // -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Written: David_Harris@hmc.edu +// Created: 9 January 2021 +// Modified: 18 January 2023 // // Purpose: Masking and muxing for subword writes // +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv index 6167e4ea2..17eedd4c4 100644 --- a/pipelined/src/lsu/swbytemask.sv +++ b/pipelined/src/lsu/swbytemask.sv @@ -1,11 +1,14 @@ /////////////////////////////////////////// // swbytemask.sv // -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Written: David_Harris@hmc.edu +// Created: 9 January 2021 +// Modified: 18 January 2023 // // Purpose: On-chip RAM, external to core // +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University