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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
This commit is contained in:
Ross Thompson 2021-03-15 12:05:10 -05:00
commit f2a6e8c6cf
2 changed files with 8 additions and 3 deletions
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7
wally-pipelined/src/uncore/dtim.sv
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@ -40,6 +40,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] HREADTim0; logic [`XLEN-1:0] HREADTim0;
// logic [`XLEN-1:0] write; // logic [`XLEN-1:0] write;
logic [31:0] HADDRd;
logic newAdr;
logic [15:0] entry; logic [15:0] entry;
logic memread, memwrite; logic memread, memwrite;
logic [3:0] busycount; logic [3:0] busycount;
@ -48,14 +50,17 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
memread <= HSELTim & ~ HWRITE; memread <= HSELTim & ~ HWRITE;
memwrite <= HSELTim & HWRITE; memwrite <= HSELTim & HWRITE;
A <= HADDR; A <= HADDR;
HADDRd <= HADDR;
end end
assign newAdr = HADDR!=HADDRd;
// busy FSM to extend READY signal // busy FSM to extend READY signal
always_ff @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin if (~HRESETn) begin
HREADYTim <= 1; HREADYTim <= 1;
end else begin end else begin
if (HREADYTim & HSELTim) begin if ((HREADYTim | newAdr) & HSELTim) begin
busycount <= 0; busycount <= 0;
HREADYTim <= #1 0; HREADYTim <= #1 0;
end else if (~HREADYTim) begin end else if (~HREADYTim) begin

4
wally-pipelined/src/uncore/imem.sv
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@ -37,12 +37,12 @@ module imem (
logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)]; logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
`endif `endif
/* verilator lint_on UNDRIVEN */ /* verilator lint_on UNDRIVEN */
logic [28:0] adrbits; logic [31:0] adrbits; // needs to be 32 bits to index RAM
logic [`XLEN-1:0] rd; logic [`XLEN-1:0] rd;
// logic [15:0] rd2; // logic [15:0] rd2;
generate generate
if (`XLEN==32) assign adrbits = AdrF[30:2]; if (`XLEN==32) assign adrbits = AdrF[31:2];
else assign adrbits = AdrF[31:3]; else assign adrbits = AdrF[31:3];
endgenerate endgenerate