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Progress toward synthesis with parameterized design

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This commit is contained in:
David Harris 2023-07-25 05:10:53 -07:00
parent 89332c35f2
commit f2623a7229
1 changed files with 2 additions and 1 deletions
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3
synthDC/scripts/synth.tcl
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@ -25,6 +25,7 @@ set maxopt $::env(MAXOPT)
set drive $::env(DRIVE) set drive $::env(DRIVE)
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
@ -37,7 +38,7 @@ if { $saifpower == 1 } {
} }
# Verilog files # Verilog files
set my_verilog_files [glob $outputDir/hdl/*] set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
# Set toplevel # Set toplevel
set my_toplevel $::env(DESIGN) set my_toplevel $::env(DESIGN)