From f2623a72295ee4d1d2497a36f25eebf7cd3c7e3f Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Tue, 25 Jul 2023 05:10:53 -0700
Subject: [PATCH] Progress toward synthesis with parameterized design

---
 synthDC/scripts/synth.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index aea0d6f17..a7ae6ef09 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -25,6 +25,7 @@ set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
 
 eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
+eval file copy -force [glob ${hdl_src}/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
@@ -37,7 +38,7 @@ if { $saifpower == 1 } {
 }
 
 # Verilog files
-set my_verilog_files [glob $outputDir/hdl/*]
+set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel
 set my_toplevel $::env(DESIGN)