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Modified fpga config to support two fpga boards with different amount of memory.

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Modified vcu108 constraints to better constrain the spi clock and in/out.
This commit is contained in:
Rose Thompson 2024-08-29 16:12:58 -07:00
parent cb05697698
commit f1d9e18dee
5 changed files with 29 additions and 16 deletions
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8
config/derivlist.txt
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@ -54,11 +54,17 @@ UNCORE_RAM_RANGE 64'h1FFF
BOOTROM_RANGE 64'hFFF BOOTROM_RANGE 64'hFFF
EXT_MEM_SUPPORTED 1 EXT_MEM_SUPPORTED 1
EXT_MEM_BASE 64'h80000000 EXT_MEM_BASE 64'h80000000
EXT_MEM_RANGE 64'h0FFFFFFF EXT_MEM_RANGE 64'h7FFFFFFF
SDC_SUPPORTED 1 SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20 PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12 BPRED_SIZE 32'd12
deriv fpgaArtyA7 fpga
EXT_MEM_RANGE 64'h0FFFFFFF
deriv fpgavcu108 fpga
EXT_MEM_RANGE 64'h7FFFFFFF
# The syn configurations are trimmed down for faster synthesis. # The syn configurations are trimmed down for faster synthesis.
deriv syn_rv32e rv32e deriv syn_rv32e rv32e
DTIM_RANGE 64'h1FF DTIM_RANGE 64'h1FF

18
fpga/constraints/constraints-vcu108.xdc
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@ -83,12 +83,20 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
##### SD Card I/O ##### ##### SD Card I/O #####
# create the generated SPICLK # create the generated SPICLK
#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK]
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}] set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}]
set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}] set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}] set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCIn}]
set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCIn}]
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCD}]
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCD}]
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}]
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}]
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}]
create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK]
set_clock_latency -source -max 3.0 [get_ports SDCCLK]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]

8
fpga/generator/Makefile
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@ -36,10 +36,6 @@ IP_Arty: $(dst)/sysrst.log \
$(dst)/xlnx_mmcm.log \ $(dst)/xlnx_mmcm.log \
$(dst)/clkconverter.log \ $(dst)/clkconverter.log \
$(dst)/ahbaxibridge.log $(dst)/ahbaxibridge.log
#$(dst)/xlnx_axi_crossbar.log \
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
#$(dst)/xlnx_axi_prtcl_conv.log
# Generate Memory IP Blocks # Generate Memory IP Blocks
.PHONY: MEM_VCU MEM_Arty .PHONY: MEM_VCU MEM_Arty
@ -57,10 +53,8 @@ PreProcessFiles:
cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/ mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
./insert_debug_comment.sh ./insert_debug_comment.sh
# modify config *** RT: eventually setup for variably defined sized memory
#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA # This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv

7
fpga/src/fpgaTop.sv
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@ -182,6 +182,7 @@ module fpgaTop
logic [511 : 0] dbg_bus; logic [511 : 0] dbg_bus;
logic CLK208; logic CLK208;
logic SDCCLKInternal;
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
assign GPO = GPIOOUT[4:0]; assign GPO = GPIOOUT[4:0];
@ -215,7 +216,11 @@ module fpgaTop
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall));
// *** these are different for different fpga ugh.
ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0),
.D2(1'b1), .SR('0));
// ahb lite to axi bridge // ahb lite to axi bridge
ahbaxibridge ahbaxibridge ahbaxibridge ahbaxibridge

2
linux/devicetree/wally-vcu108.dts
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@ -15,7 +15,7 @@
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x00 0x80000000 0x00 0x10000000>; reg = <0x00 0x80000000 0x00 0x80000000>;
}; };
cpus { cpus {