From f1d9e18dee46e0913f5168506643b018ebe80c48 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 29 Aug 2024 16:12:58 -0700 Subject: [PATCH] Modified fpga config to support two fpga boards with different amount of memory. Modified vcu108 constraints to better constrain the spi clock and in/out. --- config/derivlist.txt | 8 +++++++- fpga/constraints/constraints-vcu108.xdc | 18 +++++++++++++----- fpga/generator/Makefile | 8 +------- fpga/src/fpgaTop.sv | 9 +++++++-- linux/devicetree/wally-vcu108.dts | 2 +- 5 files changed, 29 insertions(+), 16 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index ab9ee703f..08b2fe1ec 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -54,11 +54,17 @@ UNCORE_RAM_RANGE 64'h1FFF BOOTROM_RANGE 64'hFFF EXT_MEM_SUPPORTED 1 EXT_MEM_BASE 64'h80000000 -EXT_MEM_RANGE 64'h0FFFFFFF +EXT_MEM_RANGE 64'h7FFFFFFF SDC_SUPPORTED 1 PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 +deriv fpgaArtyA7 fpga +EXT_MEM_RANGE 64'h0FFFFFFF + +deriv fpgavcu108 fpga +EXT_MEM_RANGE 64'h7FFFFFFF + # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e DTIM_RANGE 64'h1FF diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 3fbb95f68..0defeeb10 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -83,12 +83,20 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### # create the generated SPICLK -#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] +create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] -set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}] -set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}] -set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}] +set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCD}] +set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCD}] +set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}] +set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}] +set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}] +create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK] +set_clock_latency -source -max 3.0 [get_ports SDCCLK] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 1d0fcc6bc..e311729f6 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -36,10 +36,6 @@ IP_Arty: $(dst)/sysrst.log \ $(dst)/xlnx_mmcm.log \ $(dst)/clkconverter.log \ $(dst)/ahbaxibridge.log -#$(dst)/xlnx_axi_crossbar.log \ -#$(dst)/xlnx_axi_dwidth_conv_32to64.log \ -#$(dst)/xlnx_axi_dwidth_conv_64to32.log \ -#$(dst)/xlnx_axi_prtcl_conv.log # Generate Memory IP Blocks .PHONY: MEM_VCU MEM_Arty @@ -57,10 +53,8 @@ PreProcessFiles: cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi mkdir ../src/CopiedFiles_do_not_add_to_repo/config/ - cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ + cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ ./insert_debug_comment.sh - # modify config *** RT: eventually setup for variably defined sized memory - #sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # This line allows the Bootloader to be loaded in a Block RAM on the FPGA sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 9ae282966..0ecce067b 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -182,6 +182,7 @@ module fpgaTop logic [511 : 0] dbg_bus; logic CLK208; + logic SDCCLKInternal; assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPO = GPIOOUT[4:0]; @@ -215,8 +216,12 @@ module fpgaTop .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); - + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall)); + + // *** these are different for different fpga ugh. + ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0), + .D2(1'b1), .SR('0)); + // ahb lite to axi bridge ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index 01deddc6e..211631345 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -15,7 +15,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00 0x80000000 0x00 0x10000000>; + reg = <0x00 0x80000000 0x00 0x80000000>; }; cpus {