Working MIE timer tests

wally-pipelined/testbench/testbench-imperas.sv

@@ -355,7 +355,8 @@ module testbench();
     "rv64p/WALLY-MIMPID", "4000",
     "rv64p/WALLY-MHARTID", "4000",
     "rv64p/WALLY-MVENDORID", "4000",
-    "rv64p/WALLY-MEDELEG", "2000"
+    "rv64p/WALLY-MEDELEG", "2000",
+    "rv64p/WALLY-MIE", "3000"
   };
 
   string tests32p[] = '{

wally-pipelined/testgen/privileged/testgen-IE.py

@@ -20,84 +20,91 @@ from random import getrandbits
 # functions
 ##################################
 
-def writeTrapHandlers(storecmd):
+def writeTrapHandlers(storecmd, mode):
   global testnum
   [reg1, reg2, reg3] = [30, 29, 28]
   [reg4, reg5] = [27, 26]
-  lines = "\n# Trap Handler: Machine Timer Interupt\n"
+  if mode == "M":
-  lines += "_timerM_trap_handler:\n"
+    lines = "\n# Trap Handler: Machine Timer Interupt\n"
-  lines += "li x" + str(reg1) + ", MASK_XLEN(0x2A)\n"
+    lines += "_timerM_trap_handler:\n"
-  lines += "la x" + str(reg2) + ", 0x2004000\n"
+    lines += "li x" + str(reg1) + ", MASK_XLEN(0xFFFF)\n"
-  lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
+    lines += "la x" + str(reg2) + ", 0x2004000\n"
-  lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
+    lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
-  lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+    lines += "csrrc x" + str(reg3) + ", mepc, x0\n"
-  lines += "mret\n"
+    lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+    lines += "csrrw x0, mepc, x" + str(reg3) + "\n"
+    # clear machine timer interupt enable bit in mie
+    lines += "li x" + str(reg4) + ", MASK_XLEN(" + str(0x80) + ")\n"
+    lines += "csrrc x0, mie, x" + str(reg4) + "\n"
+    lines += "mret\n"
+  elif mode == "S":
+    lines = "\n# Trap Handler: Supervisor Timer Interupt\n"
+    lines += "_timerS_trap_handler:\n"
+    lines += "li x" + str(reg4) + ", MASK_XLEN(0x20)\n"
+    lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+    lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+    lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+    lines += "mret\n"
 
-  lines += "\n# Trap Handler: Supervisor Timer Interupt\n"
+  #lines += "\n# Trap Handler: User Timer Interupt\n"
-  lines += "_timerS_trap_handler:\n"
+  #lines += "_timerU_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x20)\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x10)\n"
-  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
+  #lines += "mret\n"
 
-  lines += "\n# Trap Handler: User Timer Interupt\n"
+  #lines += "\n# Trap Handler: Machine Software Interupt\n"
-  lines += "_timerU_trap_handler:\n"
+  #lines += "_softwareM_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x10)\n"
-  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
-
-  lines += "\n# Trap Handler: Machine Software Interupt\n"
-  lines += "_softwareM_trap_handler:\n"
-  lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
-  lines += "la x" + str(reg2) + ", 0x2000000\n"
-  lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
-  lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
-
-  lines += "\n# Trap Handler: Supervisor Software Interupt\n"
-  lines += "_softwareS_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x2)\n"
-  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
-
-  lines += "\n# Trap Handler: User Software Interupt\n"
-  lines += "_softwareU_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x1)\n"
-  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
-
-  lines += "\n# Trap Handler: Machine External Interupt\n"
-  lines += "_externalM_trap_handler:\n"
   #lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
   #lines += "la x" + str(reg2) + ", 0x2000000\n"
   #lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
-  lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
+  ##lines += "csrrs x" + str(reg3) + ", mepc, x0\n"
-  lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+  #lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
-  lines += "mret\n"
+  #lines += "csrrw x0, mepc, x" + str(reg3) + "\n"
+  #lines += "mret\n"
 
-  lines += "\n# Trap Handler: Supervisor External Interupt\n"
+  """lines += "\n# Trap Handler: Supervisor Software Interupt\n"
-  lines += "_externalS_trap_handler:\n"
+  lines += "_softwareS_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x200)\n"
+  lines += "li x" + str(reg4) + ", MASK_XLEN(0x2)\n"
   lines += "csrrc x0, mip, x" + str(reg4) + "\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  lines += "csrrs x" + str(reg5) + ", mepc, x0\n"
   lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  lines += "csrrw x0, mepc, x" + str(reg5) + "\n"
   lines += "mret\n"
+"""
+  #lines += "\n# Trap Handler: User Software Interupt\n"
+  #lines += "_softwareU_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x1)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
 
-  lines += "\n# Trap Handler: User External Interupt\n"
+  #lines += "\n# Trap Handler: Machine External Interupt\n"
-  lines += "_externalU_trap_handler:\n"
+  #lines += "_externalM_trap_handler:\n"
-  lines += "li x" + str(reg4) + ", MASK_XLEN(0x100)\n"
+  #lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
-  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "la x" + str(reg2) + ", 0x2000000\n"
-  lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
-  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
-  lines += "mret\n"
+  #lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: Supervisor External Interupt\n"
+  #lines += "_externalS_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x200)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: User External Interupt\n"
+  #lines += "_externalU_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x100)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
 
   f.write(lines)
 
@@ -156,26 +163,32 @@ def getMcause():
 def writeVectors(a, xlen, storecmd):
   global testnum
 
-  [reg1, reg2, reg3] = [1, 2, 3]
+  # Registers used:
+  # x13 ---> read mcause value
+  # x12 ---> save old value of mtvec
+  # x8  ---> holds mieE
+  # x5  ---> holds value of trap handler
+  # x3  ---> holds mstatusE
+  # remaining registers (not used by mode management) are free to be used by tests
+
+  [reg2, reg3] = [2, 3]
   [reg5, reg8] = [5, 8]
-  [reg9, reg10, reg11, reg12] = [9, 10, 11, 12]
+  [reg10, reg11, reg12] = [10, 11, 12]
+  [reg13, reg14, reg15] = [13, 14, 15]
 
   lines = f"\n# Testcase {testnum}: {test} Interupt\n"
   
   # mcause code
   expected = getMcause()
-  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(expected) + ")\n"
-
-  if (testnum == 0): expected = 0
 
   [mstatusE, mieE] = getInteruptEnableValues()
-  # set interupt enable bit in mstatus
+  # ensure interupt enable bit in mie is low
-  lines += "li x" + str(reg3) + ", MASK_XLEN(" + str(mstatusE) + ")\n"
+  lines += "li x" + str(reg8) + ", MASK_XLEN(" + formatstr.format(mieE) + ")\n"
-  lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
+  lines += "csrrc x0, mie, x" + str(reg8) + "\n"
 
-  # set timer interupt enable bit in mie
+  # set interupt enable bit in mstatus
-  lines += "li x" + str(reg9) + ", MASK_XLEN(" + str(mieE) + ")\n"
+  lines += "li x" + str(reg3) + ", MASK_XLEN(" + formatstr.format(mstatusE) + ")\n"
-  lines += "csrrs x0, mie, x" + str(reg3) + "\n"
+  lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
 
   # Save and set trap handler address for interrupt
   lines += "la x" + str(reg5) + ", _" + test + "_trap_handler\n"
@@ -185,59 +198,50 @@ def writeVectors(a, xlen, storecmd):
   
   # cause timer interupt
   if test == "timerM":
-    lines += "li x" + str(reg8) + ", MASK_XLEN(0)\n"
-    lines += str(storecmd) + " x" + str(reg8) + ", " + str(wordsize*testnum)+ "(x6)\n"
     
-    lines += "la x" + str(reg8) + ", 0x2004000\n"
+    # load MTIMECMP register address
+    lines += "la x" + str(reg2) + ", 0x2004000\n"
 
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0)\n"
+    # to be stored in MTIMECMP
+    lines += "li x" + str(reg10) + ", MASK_XLEN(0)\n"
 
     # save old value of mtimecmp and then set mtimecmp to zero
-    lines += "lw x" + str(reg11) + ", 0(x" + str(reg8) + ")\n"
+    if xlens == 64:
-    lines += str(storecmd) + " x" + str(reg3) + ",  0(x" + str(reg8) + ")\n"
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+
+    elif xlen == 32:
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  4(x" + str(reg2) + ")\n"
+
   elif test == "timerS":
     lines += "li x" + str(reg3) + ", MASK_XLEN(0x20)\n"
     lines += "csrrs x0, mip, x" + str(reg3) + "\n"
-  elif test == "timerU":
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0x10)\n"
-    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
   
   # cause software interupt
   if test == "softwareM":
     lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
+    lines += "li x" + str(reg11) + ", MASK_XLEN(0x1)\n"
-    lines += str(storecmd) + " x" + str(reg3) + ",  0(x" + str(reg8) + ")\n"
+    lines += str(storecmd) + " x" + str(reg11) + ",  0(x" + str(reg8) + ")\n"
   elif test == "softwareS":
     lines += "li x" + str(reg3) + ", MASK_XLEN(0x2)\n"
     lines += "csrrs x0, mip, x" + str(reg3) + "\n"
-  elif test == "softwareU":
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
-    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
   
-  # cause external interupt
-  # Not sure how to cause an external machine interupt yet
-  # will writing to PLIC just cause it? (where is the ExtIntM located in PLIC)
-  #if test == "externalM":
-    #lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
-    #lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
-    #lines += str(storecmd) + " x" + str(reg3) + ",  0(x" + str(reg8) + ")\n"
-  if test == "externalS":
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0x200)\n"
-    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
-  elif test == "externalU":
-    lines += "li x" + str(reg3) + ", MASK_XLEN(0x100)\n"
-    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
 
-  #lines += "wfi\n" # wait for interupt to be taken
+  # set timer interupt enable bit in mie
+  lines += "csrrs x0, mie, x" + str(reg8) + "\n"
+  
+  # wait for interupt to be taken
   lines += "nop\nnop\n"
 
-  lines += "csrrw " + " x" + str(reg2) + ", mcause, x" + str(reg1) + "\n"
+  lines += "csrrs " + " x" + str(reg13) + ", mcause, x0\n"
 
   # reset mtvec
   lines += "csrrw x0, mtvec, x" + str(reg12) + "\n"
 
-  lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += storecmd + " x" + str(reg13) + ", " + str(wordsize*testnum) + "(x6)\n"
-  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg2) +", "+formatstr.format(expected)+")\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg13) +", "+formatstr.format(expected)+")\n"
   f.write(lines)
   if (xlen == 32):
     line = formatrefstr.format(expected)+"\n"
@@ -251,9 +255,10 @@ def writeVectors(a, xlen, storecmd):
 ##################################
 
 # change these to suite your tests
-tests = ["timerM"] #, "timerS", "timerU", "softwareM", "softwareS", "softwareU"]
+tests = ["timerM"] #, "timerM", "timerS", "softwareM", "softwareS"]
 author = "ushakya@hmc.edu"
-xlens = [64, 32]
+xlens = [64] #, 32]
+modes = ["M"]#, "S"]
 numrand = 100;
 
 # setup
@@ -270,9 +275,9 @@ for xlen in xlens:
   else:
     storecmd = "sd"
     wordsize = 8
-  for test in tests:
+  for mode in modes:
     imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
-    basename = "WALLY-IE" 
+    basename = "WALLY-" + mode + "IE"
     fname = imperaspath + "src/" + basename + ".S"
     refname = imperaspath + "references/" + basename + ".reference_output"
     testnum = 0
@@ -292,12 +297,98 @@ for xlen in xlens:
     for line in h:  
       f.write(line)
     
-    # print directed and random test vectors
+    line = "\n"
-    for i in range(0,numrand):
+    # Registers used for dropping down to supervisor mode:
-      a = getrandbits(xlen)
+    # x30 ---> set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
-      writeVectors(a, xlen, storecmd)
+    # x20 ---> hold address of _j_all_end_{returningInstruction}
+    # x19 ---> save old value of mtvec
+    # x18 ---> save old value of medeleg
+    # x16 ---> save old value of mideleg
+    # x9  ---> bit mask for mideleg and medeleg
+    # x1  ---> used to go down to supervisor mode
 
-    writeTrapHandlers(storecmd)
+    # We need to leave at least one bit in medeleg unset so that we have a way to get
+    # back to machine mode when the tests are complete (otherwise we'll only ever be able
+    # to get up to supervisor mode). 
+    #
+    # So, we define a returning instruction which will be used to cause the exception that
+    # brings us into machine mode. The bit for this returning instruction is NOT set in
+    # medeleg. However, this also means that we can't test that instruction. So, we have
+    # two different returning instructions.
+    #
+    # Current code is written to only support ebreak and ecall.
+    #
+    # For testgen-IE, we don't need to test ebreak, so we can use that as the sole
+    # returning instruction.
+    returningInstruction = "ebreak"
+    if mode == "S":
+      # need to move down to supervisor mode (based on code in testgen-TVAL)
+      lines += f"""
+        # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
+        li x30, 0
+      """
+
+      # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
+      # back to machine mode at the end! (and we need to be in machine mode to complete the tests)
+      medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
+
+      # Set medeleg and mideleg
+      lines += f"""
+        csrr x18, medeleg
+        li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
+        csrw medeleg, x9
+
+        csrr x16, mideleg
+        li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
+        csrw mideleg, x9
+      """
+
+      # bring down to supervisor mode
+      lines += f"""
+            li x1, 0b110000000000
+            csrrc x28, mstatus, x1
+            li x1, 0b0100000000000
+            csrrs x28, mstatus, x1
+
+            auipc x1, 0
+            addi x1, x1, 16 # x1 is now right after the mret instruction
+            csrw mepc, x1
+            mret
+
+            # We're now in supervisor mode...
+          """
+
+    for test in tests:
+      # print directed and random test vectors
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        writeVectors(a, xlen, storecmd)
+
+    if mode == "S":
+      # Bring us back up to machine mode!
+      # Creates a new trap handler that just jumps to _j_all_end_{returningInstruction}
+      #
+      # Get into the trap handler by running returningInstruction (in this case its ebreak) 
+      f.write(f"""
+        li x30, 1 #may not need this 
+        csrr x19, mtvec # save old value of mtvec
+        la x20 _j_all_end_{returningInstruction}
+        csrw mtvec, x20
+        {returningInstruction}
+
+        _returnMachineMode_handler:
+        j _j_all_end_{returningInstruction}
+        mret
+
+        _j_all_end_{returningInstruction}:
+
+        # Reset trap handling csrs to old values
+        csrw mtvec, x19
+        csrw medeleg, x18
+        csrw mideleg, x16
+      """)
+    
+    f.write(lines)
 
     # print footer
     h = open("../testgen_footer.S", "r")
@@ -308,5 +399,8 @@ for xlen in xlens:
     lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
     lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
     f.write(lines)
+
+    writeTrapHandlers(storecmd, mode)
+
     f.close()
     r.close()