change message to be more apropos

This commit is contained in:
James Stine 2024-09-18 15:28:45 -05:00
parent 9e88807ad5
commit f0cb190f34

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@ -30,7 +30,7 @@ export SYN_MW=/home/jstine/MW
export SYN_memory=/home/jstine/WallyMem/rv64gc/
#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
# Environmental variables for FPGA
# Environmental variables for CTG (https://github.com/riscv-software-src/riscv-ctg)
export RISCVCTG=/home/harris/repos/riscv-ctg