mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 09:45:18 +00:00
change message to be more apropos
This commit is contained in:
parent
9e88807ad5
commit
f0cb190f34
@ -30,7 +30,7 @@ export SYN_MW=/home/jstine/MW
|
||||
export SYN_memory=/home/jstine/WallyMem/rv64gc/
|
||||
#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
|
||||
|
||||
# Environmental variables for FPGA
|
||||
# Environmental variables for CTG (https://github.com/riscv-software-src/riscv-ctg)
|
||||
export RISCVCTG=/home/harris/repos/riscv-ctg
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user