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Implemented uncached reads.

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This commit is contained in:
Ross Thompson 2021-07-13 23:03:09 -05:00
parent b6e5670bc3
commit ef598d0e79
2 changed files with 39 additions and 7 deletions
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4
wally-pipelined/regression/wave.do
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@ -401,7 +401,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/memwrite
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 297 configure wave -valuecolwidth 297
@ -417,4 +417,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {4642 ns} {4816 ns} WaveRestoreZoom {5566 ns} {5750 ns}

42
wally-pipelined/src/cache/dcache.sv vendored
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@ -90,7 +90,7 @@ module dcache
logic [BLOCKLEN-1:0] ReadDataBlockM; logic [BLOCKLEN-1:0] ReadDataBlockM;
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM, ReadDataWordMuxM;
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
logic [LOGWPL:0] FetchCount, NextFetchCount; logic [LOGWPL:0] FetchCount, NextFetchCount;
@ -111,6 +111,7 @@ module dcache
logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic [BLOCKLEN-1:0] VictimReadDataBlockM;
logic VictimDirty; logic VictimDirty;
logic SelAMOWrite; logic SelAMOWrite;
logic SelUncached;
logic [6:0] Funct7W; logic [6:0] Funct7W;
logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [2**LOGWPL-1:0] MemPAdrDecodedW;
@ -229,13 +230,19 @@ module dcache
assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
.d1(DCacheMemWriteData[`XLEN-1:0]),
.s(SelUncached),
.y(ReadDataWordMuxM));
// finally swr // finally swr
// *** BUG fix HSIZED? why was it this way? // *** BUG fix HSIZED? why was it this way?
subwordread subwordread(.HRDATA(ReadDataWordM), subwordread subwordread(.HRDATA(ReadDataWordMuxM),
.HADDRD(MemPAdrM[2:0]), .HADDRD(MemPAdrM[2:0]),
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
.HRDATAMasked(FinalReadDataWordM)); .HRDATAMasked(FinalReadDataWordM));
flopen #(`XLEN) ReadDataWReg(.clk(clk), flopen #(`XLEN) ReadDataWReg(.clk(clk),
.en(~StallW), .en(~StallW),
.d(FinalReadDataWordM), .d(FinalReadDataWordM),
@ -337,10 +344,10 @@ module dcache
STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK,
STATE_PTW_MISS_WRITE_CACHE_BLOCK, STATE_PTW_MISS_WRITE_CACHE_BLOCK,
STATE_PTW_MISS_READ_SRAM, STATE_PTW_MISS_READ_SRAM,
STATE_UNCACHED_WDV,
STATE_UNCACHED_DONE,
STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE,
STATE_UNCACHED_WRITE_DONE, STATE_UNCACHED_WRITE_DONE,
STATE_UNCACHED_READ,
STATE_UNCACHED_READ_DONE,
STATE_CPU_BUSY} statetype; STATE_CPU_BUSY} statetype;
statetype CurrState, NextState; statetype CurrState, NextState;
@ -393,6 +400,7 @@ module dcache
AHBWrite = 1'b0; AHBWrite = 1'b0;
SelAMOWrite = 1'b0; SelAMOWrite = 1'b0;
CommittedM = 1'b0; CommittedM = 1'b0;
SelUncached = 1'b0;
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
@ -438,7 +446,13 @@ module dcache
CntReset = 1'b1; CntReset = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
AHBWrite = 1'b1; AHBWrite = 1'b1;
end
// uncached read
else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
NextState = STATE_UNCACHED_READ;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBRead = 1'b1;
end end
// fault // fault
else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
@ -560,10 +574,28 @@ module dcache
end end
end end
STATE_UNCACHED_READ : begin
DCacheStall = 1'b1;
AHBRead = 1'b1;
CommittedM = 1'b1;
if(AHBAck) begin
NextState = STATE_UNCACHED_READ_DONE;
end else begin
NextState = STATE_UNCACHED_READ;
end
end
STATE_UNCACHED_WRITE_DONE: begin STATE_UNCACHED_WRITE_DONE: begin
CommittedM = 1'b1; CommittedM = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
STATE_UNCACHED_READ_DONE: begin
CommittedM = 1'b1;
SelUncached = 1'b1;
NextState = STATE_READY;
end
default: begin default: begin
end end
endcase endcase