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Remove old imperas tests

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This commit is contained in:
Jordan Carlin 2024-09-29 10:18:04 -07:00
parent 2f09369921
commit ef442808a9
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2 changed files with 105 additions and 861 deletions
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22
testbench/testbench.sv
View File

@ -5,7 +5,7 @@
// Modified:
//
// Purpose: Wally Testbench and helper modules
// Applies test programs from the riscv-arch-test and Imperas suites
// Applies test programs from the riscv-arch-test and other custom tests
//
// A component of the Wally configurable RISC-V project.
//
@ -141,7 +141,7 @@ module testbench;
case (TEST)
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (P.C_SUPPORTED)
"arch64c": if (P.ZCA_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
else tests = {arch64c};
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
@ -154,14 +154,8 @@ module testbench;
"arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt;
"arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
"arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond;
"imperas64i": tests = imperas64i;
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
"wally64q": if (P.Q_SUPPORTED) tests = wally64q;
"wally64a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally64a_lrsc;
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
"custom": tests = custom;
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
@ -207,12 +201,7 @@ module testbench;
"arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt;
"arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
"arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond;
"imperas32i": tests = imperas32i;
"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
"wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc;
"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i;
"wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph;
@ -236,6 +225,7 @@ module testbench;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
"arch32c_misalign": if (P.C_SUPPORTED) tests = arch32c_misalign;
endcase
end
if (tests.size() == 0 & ElfFile == "none") begin
@ -296,9 +286,9 @@ module testbench;
// fsm next state logic
always_comb begin
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
// and tests[0] == "2" refers to WallyRiscvArchTests
riscofTest = tests[0] == "1" | tests[0] == "2";
// riscof tests have a different signature, tests[0] == "0" refers to RiscvArchTests
// and tests[0] == "1" refers to WallyRiscvArchTests
riscofTest = tests[0] == "0" | tests[0] == "1";
pathname = tvpaths[tests[0].atoi()];
case(CurrState)

772
testbench/tests.vh
View File

@ -24,17 +24,15 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`define IMPERASTEST "0"
`define RISCVARCHTEST "1"
`define WALLYTEST "2"
`define COREMARK "3"
`define EMBENCH "4"
`define CUSTOM "5"
`define COVERAGE "6"
`define BUILDROOT "7"
`define RISCVARCHTEST "0"
`define WALLYTEST "1"
`define COREMARK "2"
`define EMBENCH "3"
`define CUSTOM "4"
`define COVERAGE "5"
`define BUILDROOT "6"
string tvpaths[] = '{
"$RISCV/imperas-riscv-tests/work/",
"../../tests/riscof/work/riscv-arch-test/",
"../../tests/riscof/work/wally-riscv-arch-test/",
"../../benchmarks/coremark/work/",
@ -183,745 +181,6 @@ string embench[] = '{
"bd_sizeopt_speed/src/wikisort/wikisort"
};
string imperas32f[] = '{
`IMPERASTEST,
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
"rv32i_m/F/FADD-S-DYN-RDN-01",
"rv32i_m/F/FADD-S-DYN-RMM-01",
"rv32i_m/F/FADD-S-DYN-RNE-01",
"rv32i_m/F/FADD-S-DYN-RTZ-01",
"rv32i_m/F/FADD-S-DYN-RUP-01",
"rv32i_m/F/FADD-S-RDN-01",
"rv32i_m/F/FADD-S-RMM-01",
"rv32i_m/F/FADD-S-RNE-01",
"rv32i_m/F/FADD-S-RTZ-01",
"rv32i_m/F/FADD-S-RUP-01",
"rv32i_m/F/FCLASS-S-01",
"rv32i_m/F/FCVT-S-W-DYN-RDN-01",
"rv32i_m/F/FCVT-S-W-DYN-RMM-01",
"rv32i_m/F/FCVT-S-W-DYN-RNE-01",
"rv32i_m/F/FCVT-S-W-DYN-RTZ-01",
"rv32i_m/F/FCVT-S-W-DYN-RUP-01",
"rv32i_m/F/FCVT-S-W-RDN-01",
"rv32i_m/F/FCVT-S-W-RMM-01",
"rv32i_m/F/FCVT-S-W-RNE-01",
"rv32i_m/F/FCVT-S-W-RTZ-01",
"rv32i_m/F/FCVT-S-W-RUP-01",
"rv32i_m/F/FCVT-S-WU-DYN-RDN-01",
"rv32i_m/F/FCVT-S-WU-DYN-RMM-01",
"rv32i_m/F/FCVT-S-WU-DYN-RNE-01",
"rv32i_m/F/FCVT-S-WU-DYN-RTZ-01",
"rv32i_m/F/FCVT-S-WU-DYN-RUP-01",
"rv32i_m/F/FCVT-S-WU-RDN-01",
"rv32i_m/F/FCVT-S-WU-RMM-01",
"rv32i_m/F/FCVT-S-WU-RNE-01",
"rv32i_m/F/FCVT-S-WU-RTZ-01",
"rv32i_m/F/FCVT-S-WU-RUP-01",
"rv32i_m/F/FCVT-W-S-DYN-RDN-01",
"rv32i_m/F/FCVT-W-S-DYN-RMM-01",
"rv32i_m/F/FCVT-W-S-DYN-RNE-01",
"rv32i_m/F/FCVT-W-S-DYN-RTZ-01",
"rv32i_m/F/FCVT-W-S-DYN-RUP-01",
"rv32i_m/F/FCVT-W-S-RDN-01",
"rv32i_m/F/FCVT-W-S-RMM-01",
"rv32i_m/F/FCVT-W-S-RNE-01",
"rv32i_m/F/FCVT-W-S-RTZ-01",
"rv32i_m/F/FCVT-W-S-RUP-01",
"rv32i_m/F/FCVT-WU-S-DYN-RDN-01",
"rv32i_m/F/FCVT-WU-S-DYN-RMM-01",
"rv32i_m/F/FCVT-WU-S-DYN-RNE-01",
"rv32i_m/F/FCVT-WU-S-DYN-RTZ-01",
"rv32i_m/F/FCVT-WU-S-DYN-RUP-01",
"rv32i_m/F/FCVT-WU-S-RDN-01",
"rv32i_m/F/FCVT-WU-S-RMM-01",
"rv32i_m/F/FCVT-WU-S-RNE-01",
"rv32i_m/F/FCVT-WU-S-RTZ-01",
"rv32i_m/F/FCVT-WU-S-RUP-01",
"rv32i_m/F/FDIV-S-DYN-RDN-01",
"rv32i_m/F/FDIV-S-DYN-RMM-01",
"rv32i_m/F/FDIV-S-DYN-RNE-01",
"rv32i_m/F/FDIV-S-DYN-RTZ-01",
"rv32i_m/F/FDIV-S-DYN-RUP-01",
"rv32i_m/F/FDIV-S-RDN-01",
"rv32i_m/F/FDIV-S-RMM-01",
"rv32i_m/F/FDIV-S-RNE-01",
"rv32i_m/F/FDIV-S-RTZ-01",
"rv32i_m/F/FDIV-S-RUP-01",
"rv32i_m/F/FEQ-S-01",
"rv32i_m/F/FLE-S-01",
"rv32i_m/F/FLT-S-01",
"rv32i_m/F/FLW-01",
"rv32i_m/F/FMADD-S-DYN-RDN-01",
"rv32i_m/F/FMADD-S-DYN-RMM-01",
"rv32i_m/F/FMADD-S-DYN-RNE-01",
"rv32i_m/F/FMADD-S-DYN-RTZ-01",
"rv32i_m/F/FMADD-S-DYN-RUP-01",
"rv32i_m/F/FMADD-S-RDN-01",
"rv32i_m/F/FMADD-S-RMM-01",
"rv32i_m/F/FMADD-S-RNE-01",
"rv32i_m/F/FMADD-S-RTZ-01",
"rv32i_m/F/FMADD-S-RUP-01",
"rv32i_m/F/FMAX-S-01",
"rv32i_m/F/FMIN-S-01",
"rv32i_m/F/FMSUB-S-DYN-RDN-01",
"rv32i_m/F/FMSUB-S-DYN-RMM-01",
"rv32i_m/F/FMSUB-S-DYN-RNE-01",
"rv32i_m/F/FMSUB-S-DYN-RTZ-01",
"rv32i_m/F/FMSUB-S-DYN-RUP-01",
"rv32i_m/F/FMSUB-S-RDN-01",
"rv32i_m/F/FMSUB-S-RMM-01",
"rv32i_m/F/FMSUB-S-RNE-01",
"rv32i_m/F/FMSUB-S-RTZ-01",
"rv32i_m/F/FMSUB-S-RUP-01",
"rv32i_m/F/FMUL-S-DYN-RDN-01",
"rv32i_m/F/FMUL-S-DYN-RMM-01",
"rv32i_m/F/FMUL-S-DYN-RNE-01",
"rv32i_m/F/FMUL-S-DYN-RTZ-01",
"rv32i_m/F/FMUL-S-DYN-RUP-01",
"rv32i_m/F/FMUL-S-RDN-01",
"rv32i_m/F/FMUL-S-RMM-01",
"rv32i_m/F/FMUL-S-RNE-01",
"rv32i_m/F/FMUL-S-RTZ-01",
"rv32i_m/F/FMUL-S-RUP-01",
"rv32i_m/F/FMV-W-X-01",
"rv32i_m/F/FMV-X-W-01",
"rv32i_m/F/FNMADD-S-DYN-RDN-01",
"rv32i_m/F/FNMADD-S-DYN-RMM-01",
"rv32i_m/F/FNMADD-S-DYN-RNE-01",
"rv32i_m/F/FNMADD-S-DYN-RTZ-01",
"rv32i_m/F/FNMADD-S-DYN-RUP-01",
"rv32i_m/F/FNMADD-S-RDN-01",
"rv32i_m/F/FNMADD-S-RMM-01",
"rv32i_m/F/FNMADD-S-RNE-01",
"rv32i_m/F/FNMADD-S-RTZ-01",
"rv32i_m/F/FNMADD-S-RUP-01",
"rv32i_m/F/FNMSUB-S-DYN-RDN-01",
"rv32i_m/F/FNMSUB-S-DYN-RMM-01",
"rv32i_m/F/FNMSUB-S-DYN-RNE-01",
"rv32i_m/F/FNMSUB-S-DYN-RTZ-01",
"rv32i_m/F/FNMSUB-S-DYN-RUP-01",
"rv32i_m/F/FNMSUB-S-RDN-01",
"rv32i_m/F/FNMSUB-S-RMM-01",
"rv32i_m/F/FNMSUB-S-RNE-01",
"rv32i_m/F/FNMSUB-S-RTZ-01",
"rv32i_m/F/FNMSUB-S-RUP-01",
"rv32i_m/F/FSGNJN-S-01",
"rv32i_m/F/FSGNJ-S-01",
"rv32i_m/F/FSGNJX-S-01",
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
"rv32i_m/F/FSQRT-S-DYN-RMM-01",
"rv32i_m/F/FSQRT-S-DYN-RNE-01",
"rv32i_m/F/FSQRT-S-DYN-RTZ-01",
"rv32i_m/F/FSQRT-S-DYN-RUP-01",
"rv32i_m/F/FSQRT-S-RDN-01",
"rv32i_m/F/FSQRT-S-RMM-01",
"rv32i_m/F/FSQRT-S-RNE-01",
"rv32i_m/F/FSQRT-S-RTZ-01",
"rv32i_m/F/FSQRT-S-RUP-01",
"rv32i_m/F/FSUB-S-DYN-RDN-01",
"rv32i_m/F/FSUB-S-DYN-RMM-01",
"rv32i_m/F/FSUB-S-DYN-RNE-01",
"rv32i_m/F/FSUB-S-DYN-RTZ-01",
"rv32i_m/F/FSUB-S-DYN-RUP-01",
"rv32i_m/F/FSUB-S-RDN-01",
"rv32i_m/F/FSUB-S-RMM-01",
"rv32i_m/F/FSUB-S-RNE-01",
"rv32i_m/F/FSUB-S-RTZ-01",
"rv32i_m/F/FSUB-S-RUP-01",
"rv32i_m/F/FSW-01"
};
string imperas64f[] = '{
`IMPERASTEST,
"rv64i_m/F/FADD-S-DYN-RDN-01",
"rv64i_m/F/FADD-S-DYN-RMM-01",
"rv64i_m/F/FADD-S-DYN-RNE-01",
"rv64i_m/F/FADD-S-DYN-RTZ-01",
"rv64i_m/F/FADD-S-DYN-RUP-01",
"rv64i_m/F/FADD-S-RDN-01",
"rv64i_m/F/FADD-S-RMM-01",
"rv64i_m/F/FADD-S-RNE-01",
"rv64i_m/F/FADD-S-RTZ-01",
"rv64i_m/F/FADD-S-RUP-01",
"rv64i_m/F/FCLASS-S-01",
"rv64i_m/F/FCVT-L-S-DYN-RDN-01",
"rv64i_m/F/FCVT-L-S-DYN-RMM-01",
"rv64i_m/F/FCVT-L-S-DYN-RNE-01",
"rv64i_m/F/FCVT-L-S-DYN-RTZ-01",
"rv64i_m/F/FCVT-L-S-DYN-RUP-01",
"rv64i_m/F/FCVT-L-S-RDN-01",
"rv64i_m/F/FCVT-L-S-RMM-01",
"rv64i_m/F/FCVT-L-S-RNE-01",
"rv64i_m/F/FCVT-L-S-RTZ-01",
"rv64i_m/F/FCVT-L-S-RUP-01",
"rv64i_m/F/FCVT-LU-S-DYN-RDN-01",
"rv64i_m/F/FCVT-LU-S-DYN-RMM-01",
"rv64i_m/F/FCVT-LU-S-DYN-RNE-01",
"rv64i_m/F/FCVT-LU-S-DYN-RTZ-01",
"rv64i_m/F/FCVT-LU-S-DYN-RUP-01",
"rv64i_m/F/FCVT-LU-S-RDN-01",
"rv64i_m/F/FCVT-LU-S-RMM-01",
"rv64i_m/F/FCVT-LU-S-RNE-01",
"rv64i_m/F/FCVT-LU-S-RTZ-01",
"rv64i_m/F/FCVT-LU-S-RUP-01",
"rv64i_m/F/FCVT-S-L-DYN-RDN-01",
"rv64i_m/F/FCVT-S-L-DYN-RMM-01",
"rv64i_m/F/FCVT-S-L-DYN-RNE-01",
"rv64i_m/F/FCVT-S-L-DYN-RTZ-01",
"rv64i_m/F/FCVT-S-L-DYN-RUP-01",
"rv64i_m/F/FCVT-S-L-RDN-01",
"rv64i_m/F/FCVT-S-L-RMM-01",
"rv64i_m/F/FCVT-S-L-RNE-01",
"rv64i_m/F/FCVT-S-L-RTZ-01",
"rv64i_m/F/FCVT-S-L-RUP-01",
"rv64i_m/F/FCVT-S-LU-DYN-RDN-01",
"rv64i_m/F/FCVT-S-LU-DYN-RMM-01",
"rv64i_m/F/FCVT-S-LU-DYN-RNE-01",
"rv64i_m/F/FCVT-S-LU-DYN-RTZ-01",
"rv64i_m/F/FCVT-S-LU-DYN-RUP-01",
"rv64i_m/F/FCVT-S-LU-RDN-01",
"rv64i_m/F/FCVT-S-LU-RMM-01",
"rv64i_m/F/FCVT-S-LU-RNE-01",
"rv64i_m/F/FCVT-S-LU-RTZ-01",
"rv64i_m/F/FCVT-S-LU-RUP-01",
"rv64i_m/F/FCVT-S-W-DYN-RDN-01",
"rv64i_m/F/FCVT-S-W-DYN-RMM-01",
"rv64i_m/F/FCVT-S-W-DYN-RNE-01",
"rv64i_m/F/FCVT-S-W-DYN-RTZ-01",
"rv64i_m/F/FCVT-S-W-DYN-RUP-01",
"rv64i_m/F/FCVT-S-W-RDN-01",
"rv64i_m/F/FCVT-S-W-RMM-01",
"rv64i_m/F/FCVT-S-W-RNE-01",
"rv64i_m/F/FCVT-S-W-RTZ-01",
"rv64i_m/F/FCVT-S-W-RUP-01",
"rv64i_m/F/FCVT-S-WU-DYN-RDN-01",
"rv64i_m/F/FCVT-S-WU-DYN-RMM-01",
"rv64i_m/F/FCVT-S-WU-DYN-RNE-01",
"rv64i_m/F/FCVT-S-WU-DYN-RTZ-01",
"rv64i_m/F/FCVT-S-WU-DYN-RUP-01",
"rv64i_m/F/FCVT-S-WU-RDN-01",
"rv64i_m/F/FCVT-S-WU-RMM-01",
"rv64i_m/F/FCVT-S-WU-RNE-01",
"rv64i_m/F/FCVT-S-WU-RTZ-01",
"rv64i_m/F/FCVT-S-WU-RUP-01",
"rv64i_m/F/FCVT-W-S-DYN-RDN-01",
"rv64i_m/F/FCVT-W-S-DYN-RMM-01",
"rv64i_m/F/FCVT-W-S-DYN-RNE-01",
"rv64i_m/F/FCVT-W-S-DYN-RTZ-01",
"rv64i_m/F/FCVT-W-S-DYN-RUP-01",
"rv64i_m/F/FCVT-W-S-RDN-01",
"rv64i_m/F/FCVT-W-S-RMM-01",
"rv64i_m/F/FCVT-W-S-RNE-01",
"rv64i_m/F/FCVT-W-S-RTZ-01",
"rv64i_m/F/FCVT-W-S-RUP-01",
"rv64i_m/F/FCVT-WU-S-DYN-RDN-01",
"rv64i_m/F/FCVT-WU-S-DYN-RMM-01",
"rv64i_m/F/FCVT-WU-S-DYN-RNE-01",
"rv64i_m/F/FCVT-WU-S-DYN-RTZ-01",
"rv64i_m/F/FCVT-WU-S-DYN-RUP-01",
"rv64i_m/F/FCVT-WU-S-RDN-01",
"rv64i_m/F/FCVT-WU-S-RMM-01",
"rv64i_m/F/FCVT-WU-S-RNE-01",
"rv64i_m/F/FCVT-WU-S-RTZ-01",
"rv64i_m/F/FCVT-WU-S-RUP-01",
"rv64i_m/F/FDIV-S-DYN-RDN-01",
"rv64i_m/F/FDIV-S-DYN-RMM-01",
"rv64i_m/F/FDIV-S-DYN-RNE-01",
"rv64i_m/F/FDIV-S-DYN-RTZ-01",
"rv64i_m/F/FDIV-S-DYN-RUP-01",
"rv64i_m/F/FDIV-S-RDN-01",
"rv64i_m/F/FDIV-S-RMM-01",
"rv64i_m/F/FDIV-S-RNE-01",
"rv64i_m/F/FDIV-S-RTZ-01",
"rv64i_m/F/FDIV-S-RUP-01",
"rv64i_m/F/FEQ-S-01",
"rv64i_m/F/FLE-S-01",
"rv64i_m/F/FLT-S-01",
"rv64i_m/F/FLW-01",
"rv64i_m/F/FMADD-S-DYN-RDN-01",
"rv64i_m/F/FMADD-S-DYN-RMM-01",
"rv64i_m/F/FMADD-S-DYN-RNE-01",
"rv64i_m/F/FMADD-S-DYN-RTZ-01",
"rv64i_m/F/FMADD-S-DYN-RUP-01",
"rv64i_m/F/FMADD-S-RDN-01",
"rv64i_m/F/FMADD-S-RMM-01",
"rv64i_m/F/FMADD-S-RNE-01",
"rv64i_m/F/FMADD-S-RTZ-01",
"rv64i_m/F/FMADD-S-RUP-01",
"rv64i_m/F/FMAX-S-01",
"rv64i_m/F/FMIN-S-01",
"rv64i_m/F/FMSUB-S-DYN-RDN-01",
"rv64i_m/F/FMSUB-S-DYN-RMM-01",
"rv64i_m/F/FMSUB-S-DYN-RNE-01",
"rv64i_m/F/FMSUB-S-DYN-RTZ-01",
"rv64i_m/F/FMSUB-S-DYN-RUP-01",
"rv64i_m/F/FMSUB-S-RDN-01",
"rv64i_m/F/FMSUB-S-RMM-01",
"rv64i_m/F/FMSUB-S-RNE-01",
"rv64i_m/F/FMSUB-S-RTZ-01",
"rv64i_m/F/FMSUB-S-RUP-01",
"rv64i_m/F/FMUL-S-DYN-RDN-01",
"rv64i_m/F/FMUL-S-DYN-RMM-01",
"rv64i_m/F/FMUL-S-DYN-RNE-01",
"rv64i_m/F/FMUL-S-DYN-RTZ-01",
"rv64i_m/F/FMUL-S-DYN-RUP-01",
"rv64i_m/F/FMUL-S-RDN-01",
"rv64i_m/F/FMUL-S-RMM-01",
"rv64i_m/F/FMUL-S-RNE-01",
"rv64i_m/F/FMUL-S-RTZ-01",
"rv64i_m/F/FMUL-S-RUP-01",
"rv64i_m/F/FMV-W-X-01",
"rv64i_m/F/FMV-X-W-01",
"rv64i_m/F/FNMADD-S-DYN-RDN-01",
"rv64i_m/F/FNMADD-S-DYN-RMM-01",
"rv64i_m/F/FNMADD-S-DYN-RNE-01",
"rv64i_m/F/FNMADD-S-DYN-RTZ-01",
"rv64i_m/F/FNMADD-S-DYN-RUP-01",
"rv64i_m/F/FNMADD-S-RDN-01",
"rv64i_m/F/FNMADD-S-RMM-01",
"rv64i_m/F/FNMADD-S-RNE-01",
"rv64i_m/F/FNMADD-S-RTZ-01",
"rv64i_m/F/FNMADD-S-RUP-01",
"rv64i_m/F/FNMSUB-S-DYN-RDN-01",
"rv64i_m/F/FNMSUB-S-DYN-RMM-01",
"rv64i_m/F/FNMSUB-S-DYN-RNE-01",
"rv64i_m/F/FNMSUB-S-DYN-RTZ-01",
"rv64i_m/F/FNMSUB-S-DYN-RUP-01",
"rv64i_m/F/FNMSUB-S-RDN-01",
"rv64i_m/F/FNMSUB-S-RMM-01",
"rv64i_m/F/FNMSUB-S-RNE-01",
"rv64i_m/F/FNMSUB-S-RTZ-01",
"rv64i_m/F/FNMSUB-S-RUP-01",
"rv64i_m/F/FSGNJN-S-01",
"rv64i_m/F/FSGNJ-S-01",
"rv64i_m/F/FSGNJX-S-01",
"rv64i_m/F/FSQRT-S-DYN-RDN-01",
"rv64i_m/F/FSQRT-S-DYN-RMM-01",
"rv64i_m/F/FSQRT-S-DYN-RNE-01",
"rv64i_m/F/FSQRT-S-DYN-RTZ-01",
"rv64i_m/F/FSQRT-S-DYN-RUP-01",
"rv64i_m/F/FSQRT-S-RDN-01",
"rv64i_m/F/FSQRT-S-RMM-01",
"rv64i_m/F/FSQRT-S-RNE-01",
"rv64i_m/F/FSQRT-S-RTZ-01",
"rv64i_m/F/FSQRT-S-RUP-01",
"rv64i_m/F/FSUB-S-DYN-RDN-01",
"rv64i_m/F/FSUB-S-DYN-RMM-01",
"rv64i_m/F/FSUB-S-DYN-RNE-01",
"rv64i_m/F/FSUB-S-DYN-RTZ-01",
"rv64i_m/F/FSUB-S-DYN-RUP-01",
"rv64i_m/F/FSUB-S-RDN-01",
"rv64i_m/F/FSUB-S-RMM-01",
"rv64i_m/F/FSUB-S-RNE-01",
"rv64i_m/F/FSUB-S-RTZ-01",
"rv64i_m/F/FSUB-S-RUP-01",
"rv64i_m/F/FSW-01"
};
string imperas64d[] = '{
`IMPERASTEST,
"rv64i_m/D/FADD-D-DYN-RDN-01",
"rv64i_m/D/FADD-D-DYN-RMM-01",
"rv64i_m/D/FADD-D-DYN-RNE-01",
"rv64i_m/D/FADD-D-DYN-RTZ-01",
"rv64i_m/D/FADD-D-DYN-RUP-01",
"rv64i_m/D/FADD-D-RDN-01",
"rv64i_m/D/FADD-D-RMM-01",
"rv64i_m/D/FADD-D-RNE-01",
"rv64i_m/D/FADD-D-RTZ-01",
"rv64i_m/D/FADD-D-RUP-01",
"rv64i_m/D/FCLASS-D-01",
"rv64i_m/D/FCVT-D-L-DYN-RDN-01",
"rv64i_m/D/FCVT-D-L-DYN-RMM-01",
"rv64i_m/D/FCVT-D-L-DYN-RNE-01",
"rv64i_m/D/FCVT-D-L-DYN-RTZ-01",
"rv64i_m/D/FCVT-D-L-DYN-RUP-01",
"rv64i_m/D/FCVT-D-L-RDN-01",
"rv64i_m/D/FCVT-D-L-RMM-01",
"rv64i_m/D/FCVT-D-L-RNE-01",
"rv64i_m/D/FCVT-D-L-RTZ-01",
"rv64i_m/D/FCVT-D-L-RUP-01",
"rv64i_m/D/FCVT-D-LU-DYN-RDN-01",
"rv64i_m/D/FCVT-D-LU-DYN-RMM-01",
"rv64i_m/D/FCVT-D-LU-DYN-RNE-01",
"rv64i_m/D/FCVT-D-LU-DYN-RTZ-01",
"rv64i_m/D/FCVT-D-LU-DYN-RUP-01",
"rv64i_m/D/FCVT-D-LU-RDN-01",
"rv64i_m/D/FCVT-D-LU-RMM-01",
"rv64i_m/D/FCVT-D-LU-RNE-01",
"rv64i_m/D/FCVT-D-LU-RTZ-01",
"rv64i_m/D/FCVT-D-LU-RUP-01",
"rv64i_m/D/FCVT-D-S-01",
"rv64i_m/D/FCVT-D-W-01",
"rv64i_m/D/FCVT-D-WU-01",
"rv64i_m/D/FCVT-L-D-DYN-RDN-01",
"rv64i_m/D/FCVT-L-D-DYN-RMM-01",
"rv64i_m/D/FCVT-L-D-DYN-RNE-01",
"rv64i_m/D/FCVT-L-D-DYN-RTZ-01",
"rv64i_m/D/FCVT-L-D-DYN-RUP-01",
"rv64i_m/D/FCVT-L-D-RDN-01",
"rv64i_m/D/FCVT-L-D-RMM-01",
"rv64i_m/D/FCVT-L-D-RNE-01",
"rv64i_m/D/FCVT-L-D-RTZ-01",
"rv64i_m/D/FCVT-L-D-RUP-01",
"rv64i_m/D/FCVT-LU-D-DYN-RDN-01",
"rv64i_m/D/FCVT-LU-D-DYN-RMM-01",
"rv64i_m/D/FCVT-LU-D-DYN-RNE-01",
"rv64i_m/D/FCVT-LU-D-DYN-RTZ-01",
"rv64i_m/D/FCVT-LU-D-DYN-RUP-01",
"rv64i_m/D/FCVT-LU-D-RDN-01",
"rv64i_m/D/FCVT-LU-D-RMM-01",
"rv64i_m/D/FCVT-LU-D-RNE-01",
"rv64i_m/D/FCVT-LU-D-RTZ-01",
"rv64i_m/D/FCVT-LU-D-RUP-01",
"rv64i_m/D/FCVT-S-D-DYN-RDN-01",
"rv64i_m/D/FCVT-S-D-DYN-RMM-01",
"rv64i_m/D/FCVT-S-D-DYN-RNE-01",
"rv64i_m/D/FCVT-S-D-DYN-RTZ-01",
"rv64i_m/D/FCVT-S-D-DYN-RUP-01",
"rv64i_m/D/FCVT-S-D-RDN-01",
"rv64i_m/D/FCVT-S-D-RMM-01",
"rv64i_m/D/FCVT-S-D-RNE-01",
"rv64i_m/D/FCVT-S-D-RTZ-01",
"rv64i_m/D/FCVT-S-D-RUP-01",
"rv64i_m/D/FCVT-W-D-DYN-RDN-01",
"rv64i_m/D/FCVT-W-D-DYN-RMM-01",
"rv64i_m/D/FCVT-W-D-DYN-RNE-01",
"rv64i_m/D/FCVT-W-D-DYN-RTZ-01",
"rv64i_m/D/FCVT-W-D-DYN-RUP-01",
"rv64i_m/D/FCVT-W-D-RDN-01",
"rv64i_m/D/FCVT-W-D-RMM-01",
"rv64i_m/D/FCVT-W-D-RNE-01",
"rv64i_m/D/FCVT-W-D-RTZ-01",
"rv64i_m/D/FCVT-W-D-RUP-01",
"rv64i_m/D/FCVT-WU-D-DYN-RDN-01",
"rv64i_m/D/FCVT-WU-D-DYN-RMM-01",
"rv64i_m/D/FCVT-WU-D-DYN-RNE-01",
"rv64i_m/D/FCVT-WU-D-DYN-RTZ-01",
"rv64i_m/D/FCVT-WU-D-DYN-RUP-01",
"rv64i_m/D/FCVT-WU-D-RDN-01",
"rv64i_m/D/FCVT-WU-D-RMM-01",
"rv64i_m/D/FCVT-WU-D-RNE-01",
"rv64i_m/D/FCVT-WU-D-RTZ-01",
"rv64i_m/D/FCVT-WU-D-RUP-01",
"rv64i_m/D/FDIV-D-DYN-RDN-01",
"rv64i_m/D/FDIV-D-DYN-RMM-01",
"rv64i_m/D/FDIV-D-DYN-RNE-01",
"rv64i_m/D/FDIV-D-DYN-RTZ-01",
"rv64i_m/D/FDIV-D-DYN-RUP-01",
"rv64i_m/D/FDIV-D-RDN-01",
"rv64i_m/D/FDIV-D-RMM-01",
"rv64i_m/D/FDIV-D-RNE-01",
"rv64i_m/D/FDIV-D-RTZ-01",
"rv64i_m/D/FDIV-D-RUP-01",
"rv64i_m/D/FEQ-D-01",
"rv64i_m/D/FLD-01",
"rv64i_m/D/FLE-D-01",
"rv64i_m/D/FLT-D-01",
"rv64i_m/D/FMADD-D-DYN-RDN-01",
"rv64i_m/D/FMADD-D-DYN-RMM-01",
"rv64i_m/D/FMADD-D-DYN-RNE-01",
"rv64i_m/D/FMADD-D-DYN-RTZ-01",
"rv64i_m/D/FMADD-D-DYN-RUP-01",
"rv64i_m/D/FMADD-D-RDN-01",
"rv64i_m/D/FMADD-D-RMM-01",
"rv64i_m/D/FMADD-D-RNE-01",
"rv64i_m/D/FMADD-D-RTZ-01",
"rv64i_m/D/FMADD-D-RUP-01",
"rv64i_m/D/FMAX-D-01",
"rv64i_m/D/FMIN-D-01",
"rv64i_m/D/FMSUB-D-DYN-RDN-01",
"rv64i_m/D/FMSUB-D-DYN-RMM-01",
"rv64i_m/D/FMSUB-D-DYN-RNE-01",
"rv64i_m/D/FMSUB-D-DYN-RTZ-01",
"rv64i_m/D/FMSUB-D-DYN-RUP-01",
"rv64i_m/D/FMSUB-D-RDN-01",
"rv64i_m/D/FMSUB-D-RMM-01",
"rv64i_m/D/FMSUB-D-RNE-01",
"rv64i_m/D/FMSUB-D-RTZ-01",
"rv64i_m/D/FMSUB-D-RUP-01",
"rv64i_m/D/FMUL-D-DYN-RDN-01",
"rv64i_m/D/FMUL-D-DYN-RMM-01",
"rv64i_m/D/FMUL-D-DYN-RNE-01",
"rv64i_m/D/FMUL-D-DYN-RTZ-01",
"rv64i_m/D/FMUL-D-DYN-RUP-01",
"rv64i_m/D/FMUL-D-RDN-01",
"rv64i_m/D/FMUL-D-RMM-01",
"rv64i_m/D/FMUL-D-RNE-01",
"rv64i_m/D/FMUL-D-RTZ-01",
"rv64i_m/D/FMUL-D-RUP-01",
"rv64i_m/D/FMV-D-X-01",
"rv64i_m/D/FMV-X-D-01",
"rv64i_m/D/FNMADD-D-DYN-RDN-01",
"rv64i_m/D/FNMADD-D-DYN-RMM-01",
"rv64i_m/D/FNMADD-D-DYN-RNE-01",
"rv64i_m/D/FNMADD-D-DYN-RTZ-01",
"rv64i_m/D/FNMADD-D-DYN-RUP-01",
"rv64i_m/D/FNMADD-D-RDN-01",
"rv64i_m/D/FNMADD-D-RMM-01",
"rv64i_m/D/FNMADD-D-RNE-01",
"rv64i_m/D/FNMADD-D-RTZ-01",
"rv64i_m/D/FNMADD-D-RUP-01",
"rv64i_m/D/FNMSUB-D-DYN-RDN-01",
"rv64i_m/D/FNMSUB-D-DYN-RMM-01",
"rv64i_m/D/FNMSUB-D-DYN-RNE-01",
"rv64i_m/D/FNMSUB-D-DYN-RTZ-01",
"rv64i_m/D/FNMSUB-D-DYN-RUP-01",
"rv64i_m/D/FNMSUB-D-RDN-01",
"rv64i_m/D/FNMSUB-D-RMM-01",
"rv64i_m/D/FNMSUB-D-RNE-01",
"rv64i_m/D/FNMSUB-D-RTZ-01",
"rv64i_m/D/FNMSUB-D-RUP-01",
"rv64i_m/D/FSD-01",
"rv64i_m/D/FSGNJ-D-01",
"rv64i_m/D/FSGNJN-D-01",
"rv64i_m/D/FSGNJX-D-01",
"rv64i_m/D/FSQRT-D-DYN-RDN-01",
"rv64i_m/D/FSQRT-D-DYN-RMM-01",
"rv64i_m/D/FSQRT-D-DYN-RNE-01",
"rv64i_m/D/FSQRT-D-DYN-RTZ-01",
"rv64i_m/D/FSQRT-D-DYN-RUP-01",
"rv64i_m/D/FSQRT-D-RDN-01",
"rv64i_m/D/FSQRT-D-RMM-01",
"rv64i_m/D/FSQRT-D-RNE-01",
"rv64i_m/D/FSQRT-D-RTZ-01",
"rv64i_m/D/FSQRT-D-RUP-01",
"rv64i_m/D/FSUB-D-DYN-RDN-01",
"rv64i_m/D/FSUB-D-DYN-RMM-01",
"rv64i_m/D/FSUB-D-DYN-RNE-01",
"rv64i_m/D/FSUB-D-DYN-RTZ-01",
"rv64i_m/D/FSUB-D-DYN-RUP-01",
"rv64i_m/D/FSUB-D-RDN-01",
"rv64i_m/D/FSUB-D-RMM-01",
"rv64i_m/D/FSUB-D-RNE-01",
"rv64i_m/D/FSUB-D-RTZ-01",
"rv64i_m/D/FSUB-D-RUP-01"
};
string imperas64m[] = '{
`IMPERASTEST,
"rv64i_m/M/DIV-01",
"rv64i_m/M/DIVU-01",
"rv64i_m/M/DIVUW-01",
"rv64i_m/M/DIVW-01",
"rv64i_m/M/MUL-01",
"rv64i_m/M/MULH-01",
"rv64i_m/M/MULHSU-01",
"rv64i_m/M/MULHU-01",
"rv64i_m/M/MULW-01",
"rv64i_m/M/REM-01",
"rv64i_m/M/REMU-01",
"rv64i_m/M/REMUW-01",
"rv64i_m/M/REMW-01"
};
string imperas64c[] = '{
`IMPERASTEST,
"rv64i_m/C/C-ADD-01",
"rv64i_m/C/C-ADDI-01",
"rv64i_m/C/C-ADDI16SP-01",
"rv64i_m/C/C-ADDI4SPN-01",
"rv64i_m/C/C-ADDIW-01",
"rv64i_m/C/C-ADDW-01",
"rv64i_m/C/C-AND-01",
"rv64i_m/C/C-ANDI-01",
"rv64i_m/C/C-BEQZ-01",
"rv64i_m/C/C-BNEZ-01",
"rv64i_m/C/C-J-01",
"rv64i_m/C/C-JALR-01",
"rv64i_m/C/C-JR-01",
"rv64i_m/C/C-LD-01",
"rv64i_m/C/C-LDSP-01",
"rv64i_m/C/C-LI-01",
"rv64i_m/C/C-LUI-01",
"rv64i_m/C/C-LW-01",
"rv64i_m/C/C-LWSP-01",
"rv64i_m/C/C-MV-01",
"rv64i_m/C/C-OR-01",
"rv64i_m/C/C-SD-01",
"rv64i_m/C/C-SDSP-01",
"rv64i_m/C/C-SLLI-01",
"rv64i_m/C/C-SRAI-01",
"rv64i_m/C/C-SRLI-01",
"rv64i_m/C/C-SUB-01",
"rv64i_m/C/C-SUBW-01",
"rv64i_m/C/C-SW-01",
"rv64i_m/C/C-SWSP-01",
"rv64i_m/C/C-XOR-01",
"rv64i_m/C/I-C-EBREAK-01",
"rv64i_m/C/I-C-NOP-01"
};
string imperas64iNOc[] = {
`IMPERASTEST,
"rv64i_m/I/I-MISALIGN_JMP-01"
};
string imperas64i[] = '{
`IMPERASTEST,
"rv64i_m/I/I-DELAY_SLOTS-01",
"rv64i_m/I/ADD-01",
"rv64i_m/I/ADDI-01",
"rv64i_m/I/ADDIW-01",
"rv64i_m/I/ADDW-01",
"rv64i_m/I/AND-01",
"rv64i_m/I/ANDI-01",
"rv64i_m/I/AUIPC-01",
"rv64i_m/I/BEQ-01",
"rv64i_m/I/BGE-01",
"rv64i_m/I/BGEU-01",
"rv64i_m/I/BLT-01",
"rv64i_m/I/BLTU-01",
"rv64i_m/I/BNE-01",
"rv64i_m/I/I-DELAY_SLOTS-01",
"rv64i_m/I/I-EBREAK-01",
"rv64i_m/I/I-ECALL-01",
"rv64i_m/I/I-ENDIANESS-01",
"rv64i_m/I/I-IO-01",
// "rv64i_m/I/I-MISALIGN_JMP-01",
"rv64i_m/I/I-MISALIGN_LDST-01",
"rv64i_m/I/I-NOP-01",
"rv64i_m/I/I-RF_size-01",
"rv64i_m/I/I-RF_width-01",
"rv64i_m/I/I-RF_x0-01",
"rv64i_m/I/JAL-01",
"rv64i_m/I/JALR-01",
"rv64i_m/I/LB-01",
"rv64i_m/I/LBU-01",
"rv64i_m/I/LD-01",
"rv64i_m/I/LH-01",
"rv64i_m/I/LHU-01",
"rv64i_m/I/LUI-01",
"rv64i_m/I/LW-01",
"rv64i_m/I/LWU-01",
"rv64i_m/I/OR-01",
"rv64i_m/I/ORI-01",
"rv64i_m/I/SB-01",
"rv64i_m/I/SD-01",
"rv64i_m/I/SH-01",
"rv64i_m/I/SLL-01",
"rv64i_m/I/SLLI-01",
"rv64i_m/I/SLLIW-01",
"rv64i_m/I/SLLW-01",
"rv64i_m/I/SLT-01",
"rv64i_m/I/SLTI-01",
"rv64i_m/I/SLTIU-01",
"rv64i_m/I/SLTU-01",
"rv64i_m/I/SRA-01",
"rv64i_m/I/SRAI-01",
"rv64i_m/I/SRAIW-01",
"rv64i_m/I/SRAW-01",
"rv64i_m/I/SRL-01",
"rv64i_m/I/SRLI-01",
"rv64i_m/I/SRLIW-01",
"rv64i_m/I/SRLW-01",
"rv64i_m/I/SUB-01",
"rv64i_m/I/SUBW-01",
"rv64i_m/I/SW-01",
"rv64i_m/I/XOR-01",
"rv64i_m/I/XORI-01"
};
string imperas32m[] = '{
`IMPERASTEST,
"rv32i_m/M/DIV-01",
"rv32i_m/M/DIVU-01",
"rv32i_m/M/MUL-01",
"rv32i_m/M/MULH-01",
"rv32i_m/M/MULHSU-01",
"rv32i_m/M/MULHU-01",
"rv32i_m/M/REM-01",
"rv32i_m/M/REMU-01"
};
string imperas32c[] = '{
`IMPERASTEST,
"rv32i_m/C/C-ADD-01",
"rv32i_m/C/C-ADDI-01",
"rv32i_m/C/C-ADDI16SP-01",
"rv32i_m/C/C-ADDI4SPN-01",
"rv32i_m/C/C-AND-01",
"rv32i_m/C/C-ANDI-01",
"rv32i_m/C/C-BEQZ-01",
"rv32i_m/C/C-BNEZ-01",
"rv32i_m/C/C-J-01",
"rv32i_m/C/C-JAL-01",
"rv32i_m/C/C-JALR-01",
"rv32i_m/C/C-JR-01",
"rv32i_m/C/C-LI-01",
"rv32i_m/C/C-LUI-01",
"rv32i_m/C/C-LW-01",
"rv32i_m/C/C-LWSP-01",
"rv32i_m/C/C-MV-01",
"rv32i_m/C/C-OR-01",
"rv32i_m/C/C-SLLI-01",
"rv32i_m/C/C-SRAI-01",
"rv32i_m/C/C-SRLI-01",
"rv32i_m/C/C-SUB-01",
"rv32i_m/C/C-SW-01",
"rv32i_m/C/C-SWSP-01",
"rv32i_m/C/C-XOR-01",
"rv32i_m/C/I-C-EBREAK-01",
"rv32i_m/C/I-C-NOP-01"
};
string imperas32iNOc[] = {
`IMPERASTEST,
"rv32i_m/I/I-MISALIGN_JMP-01"
};
string imperas32i[] = {
`IMPERASTEST,
"rv32i_m/I/ADD-01",
"rv32i_m/I/ADDI-01",
"rv32i_m/I/AND-01",
"rv32i_m/I/ANDI-01",
"rv32i_m/I/AUIPC-01",
"rv32i_m/I/BEQ-01",
"rv32i_m/I/BGE-01",
"rv32i_m/I/BGEU-01",
"rv32i_m/I/BLT-01",
"rv32i_m/I/BLTU-01",
"rv32i_m/I/BNE-01",
"rv32i_m/I/I-DELAY_SLOTS-01",
"rv32i_m/I/I-EBREAK-01",
"rv32i_m/I/I-ECALL-01",
"rv32i_m/I/I-ENDIANESS-01",
"rv32i_m/I/I-IO-01",
// "rv32i_m/I/I-MISALIGN_JMP-01",
"rv32i_m/I/I-MISALIGN_LDST-01",
"rv32i_m/I/I-NOP-01",
"rv32i_m/I/I-RF_size-01",
"rv32i_m/I/I-RF_width-01",
"rv32i_m/I/I-RF_x0-01",
"rv32i_m/I/JAL-01",
"rv32i_m/I/JALR-01",
"rv32i_m/I/LB-01",
"rv32i_m/I/LBU-01",
"rv32i_m/I/LH-01",
"rv32i_m/I/LHU-01",
"rv32i_m/I/LUI-01",
"rv32i_m/I/LW-01",
"rv32i_m/I/OR-01",
"rv32i_m/I/ORI-01",
"rv32i_m/I/SB-01",
"rv32i_m/I/SH-01",
"rv32i_m/I/SLL-01",
"rv32i_m/I/SLLI-01",
"rv32i_m/I/SLT-01",
"rv32i_m/I/SLTI-01",
"rv32i_m/I/SLTIU-01",
"rv32i_m/I/SLTU-01",
"rv32i_m/I/SRA-01",
"rv32i_m/I/SRAI-01",
"rv32i_m/I/SRL-01",
"rv32i_m/I/SRLI-01",
"rv32i_m/I/SUB-01",
"rv32i_m/I/SW-01",
"rv32i_m/I/XOR-01",
"rv32i_m/I/XORI-01"
};
string wally64q[] = '{
`WALLYTEST,
"rv64i_m/Q/src/WALLY-q-01.S"
@ -4017,6 +3276,12 @@ string arch32c[] = '{
"rv32i_m/C/src/cxor-01.S"
};
string arch32c_misalign[] = '{
`RISCVARCHTEST,
"rv32i_m/C/src/misalign1-cjalr-01.S",
"rv32i_m/C/src/misalign1-cjr-01.S"
};
string arch32cpriv[] = '{
// `RISCVARCHTEST,
"rv32i_m/C/src/cebreak-01.S"
@ -4231,17 +3496,6 @@ string custom[] = '{
"cacheTest"
};
string testsBP64[] = '{
`IMPERASTEST,
"rv64BP/simple"
// "rv64BP/mmm",
// "rv64BP/linpack_bench",
// "rv64BP/sieve",
// "rv64BP/qsort",
// "rv64BP/dhrystone"
};
string ahb64[] = '{
`RISCVARCHTEST,
"rv64i_m/F/src/fadd_b11-01.S"