From ef442808a93f850022db91f72f2eb2d956859fbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 10:18:04 -0700 Subject: [PATCH] Remove old imperas tests --- testbench/testbench.sv | 194 +++++------ testbench/tests.vh | 772 +---------------------------------------- 2 files changed, 105 insertions(+), 861 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f91bdcc67..de627e1f8 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -2,26 +2,26 @@ // testbench.sv // // Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Modified: // // Purpose: Wally Testbench and helper modules -// Applies test programs from the riscv-arch-test and Imperas suites -// +// Applies test programs from the riscv-arch-test and other custom tests +// // A component of the Wally configurable RISC-V project. -// +// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -50,7 +50,7 @@ module testbench; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; parameter RVVI_SYNTH_SUPPORTED=0; - + `ifdef USE_IMPERAS_DV import idvPkg::*; import rvviApiPkg::*; @@ -64,7 +64,7 @@ module testbench; `elsif VCS import "DPI-C" function string getenv(input string env_name); string RISCV_DIR = getenv("RISCV"); - string WALLY_DIR = getenv("WALLY"); + string WALLY_DIR = getenv("WALLY"); `else string RISCV_DIR = "$RISCV"; string WALLY_DIR = "$WALLY"; @@ -82,7 +82,7 @@ module testbench; // DUT signals logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; + logic HREADYEXT, HRESPEXT; logic [P.PA_BITS-1:0] HADDR; logic [P.AHBW-1:0] HWDATA; logic [P.XLEN/8-1:0] HWSTRB; @@ -102,12 +102,12 @@ module testbench; logic SDCCmd; logic SDCIn; logic [3:0] SDCCS; - logic SDCCLK; + logic SDCCLK; logic HREADY; logic HSELEXT; - + string ProgramAddrMapFile, ProgramLabelMapFile; integer ProgramAddrLabelArray [string]; @@ -118,7 +118,7 @@ module testbench; string tests[]; logic DCacheFlushDone, DCacheFlushStart; - logic riscofTest; + logic riscofTest; logic Validate; logic SelectTest; logic TestComplete; @@ -134,36 +134,30 @@ module testbench; if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT)) INSTR_LIMIT = 0; //$display("TEST = %s ElfFile = %s", TEST, ElfFile); - + // pick tests based on modes supported //tests = '{}; if (P.XLEN == 64) begin // RV64 case (TEST) "arch64i": tests = arch64i; "arch64priv": tests = arch64priv; - "arch64c": if (P.C_SUPPORTED) + "arch64c": if (P.ZCA_SUPPORTED) if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; "arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo; "arch64f": if (P.F_SUPPORTED) tests = arch64f; - "arch64d": if (P.D_SUPPORTED) tests = arch64d; + "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; - "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; "arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt; - "arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt; + "arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt; "arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei; "arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond; - "imperas64i": tests = imperas64i; - "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; - "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; - "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; "wally64q": if (P.Q_SUPPORTED) tests = wally64q; "wally64a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally64a_lrsc; - "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; - else tests = imperas64iNOc; "custom": tests = custom; - "wally64i": tests = wally64i; + "wally64i": tests = wally64i; "wally64priv": tests = wally64priv; "wally64periph": tests = wally64periph; "coremark": tests = coremark; @@ -177,7 +171,7 @@ module testbench; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; - "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; + "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; @@ -188,32 +182,27 @@ module testbench; "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; - endcase + endcase end else begin // RV32 case (TEST) - "arch32e": tests = arch32e; + "arch32e": tests = arch32e; "arch32i": tests = arch32i; "arch32priv": tests = arch32priv; - "arch32c": if (P.C_SUPPORTED) + "arch32c": if (P.C_SUPPORTED) if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; - "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; + "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; "arch32f": if (P.F_SUPPORTED) tests = arch32f; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; "arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt; - "arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt; + "arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt; "arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei; "arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond; - "imperas32i": tests = imperas32i; - "imperas32f": if (P.F_SUPPORTED) tests = imperas32f; - "imperas32m": if (P.M_SUPPORTED) tests = imperas32m; - "wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; - "imperas32c": if (P.C_SUPPORTED) tests = imperas32c; - else tests = imperas32iNOc; - "wally32i": tests = wally32i; + "wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; + "wally32i": tests = wally32i; "wally32priv": tests = wally32priv; "wally32periph": tests = wally32periph; "ahb32" : tests = ahb32; @@ -226,7 +215,7 @@ module testbench; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; - "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; + "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; @@ -236,6 +225,7 @@ module testbench; "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; + "arch32c_misalign": if (P.C_SUPPORTED) tests = arch32c_misalign; endcase end if (tests.size() == 0 & ElfFile == "none") begin @@ -292,13 +282,13 @@ module testbench; always_ff @(posedge clk) if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET; - else CurrState <= NextState; + else CurrState <= NextState; // fsm next state logic always_comb begin - // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests - // and tests[0] == "2" refers to WallyRiscvArchTests - riscofTest = tests[0] == "1" | tests[0] == "2"; + // riscof tests have a different signature, tests[0] == "0" refers to RiscvArchTests + // and tests[0] == "1" refers to WallyRiscvArchTests + riscofTest = tests[0] == "0" | tests[0] == "1"; pathname = tvpaths[tests[0].atoi()]; case(CurrState) @@ -321,11 +311,11 @@ module testbench; default: NextState = STATE_TESTBENCH_RESET; endcase end // always_comb - // fsm output control logic - assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | - CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | + // fsm output control logic + assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | + CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST; - // this initialization is very expensive, only do it for coremark. + // this initialization is very expensive, only do it for coremark. assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark"; assign LoadMem = CurrState == STATE_LOAD_MEMORIES; assign ResetCntRst = CurrState == STATE_INIT_TEST; @@ -356,7 +346,7 @@ module testbench; assign EcallFaultM = dut.core.priv.priv.EcallFaultM; else assign EcallFaultM = 0; - + always @(posedge clk) begin //////////////////////////////////////////////////////////////////////////////// // Verify the test ran correctly by checking the memory against a known signature. @@ -368,12 +358,12 @@ module testbench; $stop; end if(SelectTest) begin - if (riscofTest) begin + if (riscofTest) begin memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; elffilename = {pathname, tests[test], "ref/ref.elf"}; ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; - end else if(TEST == "buildroot") begin + end else if(TEST == "buildroot") begin memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; elffilename = "buildroot"; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; @@ -397,8 +387,8 @@ module testbench; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; end - // declare memory labels that interest us, the updateProgramAddrLabelArray task will find - // the addr of each label and fill the array. To expand, add more elements to this array + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find + // the addr of each label and fill the array. To expand, add more elements to this array // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray); end @@ -408,9 +398,9 @@ module testbench; $fclose(uartoutfile); if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file - // this contains instret and cycles for start and end of test run, used by embench - // python speed script to calculate embench speed score. - // also, begin_signature contains the results of the self checking mechanism, + // this contains instret and cycles for start and end of test run, used by embench + // python speed script to calculate embench speed score. + // also, begin_signature contains the results of the self checking mechanism, // which will be read by the python script for error checking $display("Embench Benchmark: %s is done.", tests[test]); if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; @@ -433,17 +423,17 @@ module testbench; `else $finish; `endif - end else begin + end else begin // for tests with no self checking mechanism, read .signature.output file and compare to check for errors // clear signature to prevent contamination from previous tests if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); - else if (TEST != "embench") begin + else if (TEST != "embench") begin CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); if(errors > 0) totalerrors = totalerrors + 1; end end - test = test + 1; + test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); @@ -473,7 +463,7 @@ module testbench; if (LoadMem) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; - sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; + sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation @@ -548,7 +538,7 @@ module testbench; end end end - end + end if (P.DTIM_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -569,9 +559,9 @@ module testbench; integer adrindex; if (P.UNCORE_RAM_SUPPORTED) - always @(posedge clk) + always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) - for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0; //////////////////////////////////////////////////////////////////////////////// @@ -584,10 +574,10 @@ module testbench; assign SPIIn = 1'b0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) - ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), + ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); - end else begin + end else begin assign HREADYEXT = 1'b1; assign {HRESPEXT, HRDATAEXT} = '0; end @@ -597,7 +587,7 @@ module testbench; /* -----\/----- EXCLUDED -----\/----- sdModel sdcard (.sdClk(SDCCLK), - .cmd(SDCCmd), + .cmd(SDCCmd), .dat(SDCDat)); assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; @@ -607,14 +597,14 @@ module testbench; -----/\----- EXCLUDED -----/\----- */ end else begin assign SDCIn = 1'b1; - + end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall), + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); + .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); // generate clock to sequence tests always begin @@ -629,17 +619,17 @@ module testbench; logic [3:0] mii_txd; logic mii_tx_en, mii_tx_er; - rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) + rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) rvvitbwrapper(.clk, .reset, .RVVIStall, .mii_tx_clk(clk), .mii_txd, .mii_tx_en, .mii_tx_er, .mii_rx_clk(clk), .mii_rxd('0), .mii_rx_dv('0), .mii_rx_er('0)); end else begin assign RVVIStall = '0; end - + /* // Print key info each cycle for debugging - always @(posedge clk) begin + always @(posedge clk) begin #2; $display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x", dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM); @@ -667,7 +657,7 @@ module testbench; // watch for problems such as lockup, reading unitialized memory, bad configs watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST); // check if PCW is stuck - ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, + ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName); riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) @@ -692,7 +682,7 @@ module testbench; end // Termination condition - // Terminate on + // Terminate on // 1. jump to self loop (0x0000006f) // 2. a store word writes to the address "tohost" // 3. or PC is stuck at 0 @@ -706,13 +696,13 @@ module testbench; // (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); // if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) // $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler."); - end + end DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); if(P.ZICSR_SUPPORTED) begin logic [P.XLEN-1:0] Minstret; - assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; always @(negedge clk) begin if (INSTR_LIMIT > 0) begin if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); @@ -758,14 +748,14 @@ end $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); $fatal; end - + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GCK")); void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, XLEN==64 ? 56 : 34)); void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); - if(elffilename == "buildroot") filename = ""; + if(elffilename == "buildroot") filename = ""; else filename = elffilename; // use the ImperasDV rvviRefInit to load the reference model with an elf file @@ -778,8 +768,8 @@ end if (!rvviRefInit("")) begin // still have to call with nothing $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); $fatal; - end - + end + memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; @@ -797,7 +787,7 @@ end //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); end $fclose(memFile); - + $display("RVVI Loading ram.bin"); memFile = $fopen(memfilenameImperasDV, "rb"); index = 'h80000000 - 8; @@ -812,9 +802,9 @@ end //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); end $fclose(memFile); - + $display("RVVI Loading Complete"); - + void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address end @@ -829,22 +819,22 @@ end void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH - void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH + void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH end // User HPMCOUNTER3 - HPMCOUNTER31 for (iter='hC03; iter<='hC1F; iter++) begin void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx - if (P.XLEN == 32) + if (P.XLEN == 32) void'(rvviRefCsrSetVolatile(0, iter+128)); // HPMCOUNTERxH - end - + end + // Machine MHPMCOUNTER3 - MHPMCOUNTER31 for (iter='hB03; iter<='hB1F; iter++) begin void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx - if (P.XLEN == 32) + if (P.XLEN == 32) void'(rvviRefCsrSetVolatile(0, iter+128)); // MHPMCOUNTERxH - end - + end + // cannot predict this register due to latency between // pending and taken void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP @@ -880,7 +870,7 @@ end end void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! - + end always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); @@ -902,7 +892,7 @@ end task automatic CheckSignature; // This task must be declared inside this module as it needs access to parameter P. There is // no way to pass P to the task unless we convert it to a module. - + input string pathname; input string TestName; input logic riscofTest; @@ -920,8 +910,8 @@ end string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; - //$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time); - + //$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time); + // read .signature.output file and compare to check for errors if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"}; else signame = {pathname, TestName, ".signature.output"}; @@ -951,8 +941,8 @@ end end // Check valid number of lines were read - if (siglines == 0) begin - errors = 1; + if (siglines == 0) begin + errors = 1; $display("Error: empty test file %s", signame); end else if (P.XLEN == 64 & (siglines % 2)) begin errors = 1; @@ -970,9 +960,9 @@ end testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); for (i=0; i