Merge pull request #618 from davidharrishmc/dev

Derived configurations, Zfh FMA tests

bin/derivgen.pl

@@ -40,6 +40,7 @@ my $curderiv = "";
 my @derivlist = ();
 my %derivs;
 my %basederiv;
+my @derivnames = ();
 
 if ($#ARGV != -1) {
     die("Usage: $0")
@@ -69,7 +70,8 @@ foreach my $line (<$fh>) {
 }
 &terminateDeriv();
 close($fh);
-foreach my $key (keys %derivs) {
+#foreach my $key (keys %derivs) {
+foreach my $key (@derivnames) {
     my $dir = "$ENV{WALLY}/config/deriv/$key";
     system("rm -rf $dir");
     system("mkdir -p $dir");
@@ -78,9 +80,9 @@ foreach my $key (keys %derivs) {
     my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh";
     if (! -e $base) {
         $base = "$ENV{WALLY}/config/deriv/$basederiv{$key}/config.vh";
-        if (! -e $base) {
+        #if (! -e $base) {
-            die("Unable to find base config $base for $key\n");
+        #    die("Unable to find base config $base for $key\n");
-        }
+        #}
     }
     system("cp $base $configunmod");
     open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!";
@@ -117,6 +119,7 @@ sub terminateDeriv {
     if ($curderiv ne "") { # close out the previous derivative
         my @dl = @derivlist;
         $derivs{$curderiv} = \@dl;
+        push(@derivnames, $curderiv);
     }
 };
 

config/shared/config-shared.vh

@@ -109,9 +109,9 @@ localparam DIVBLEN     = $clog2(DIVb+1);                            // enough bi
 localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));  // max(XLEN, NF)
 localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
 localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
-localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6)));
+localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6))); // max(CVTLEN+NF+1, DIVb + 1 + NF + 1, 3*NF+6)
 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
-localparam CORRSHIFTSZ = (((DIVMINb+1+NF) > (3*NF+4) ? (DIVMINb+1+NF) : (3*NF+4))); // max(DIVMINb+NF+1, 3*NF+4)
+localparam CORRSHIFTSZ = (NORMSHIFTSZ-2 > (DIVMINb + 1 + NF)) ? NORMSHIFTSZ-2 : (DIVMINb+1+NF);  // max(NORMSHIFTSZ-2, DIVMINb + 1 + NF)
 
 
 // Disable spurious Verilator warnings

sim/lint-wally

@@ -38,7 +38,7 @@ for config in ${configs[@]}; do
         echo -e "${GREEN}$config passed lint${NC}"
     fi
 done
-if [ $fails > 0 ]; then
+if [ $fails -gt 0 ]; then
     echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations"
     exit 1
 fi

sim/regression-wally

@@ -54,7 +54,7 @@ else:
             name="lints",
             variant="all",
             cmd="./lint-wally " + nightMode + " | tee {}",
-            grepstr="All lints run with no errors or warnings"
+            grepstr="lints run with no errors or warnings"
         )
     ]
 
@@ -88,7 +88,7 @@ for test in tests64i:
   configs.append(tc)
 
 tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
-tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"]  # "arch32zbc", "arch32zfad",
+tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"]  # "arch32zbc", "arch32zfad",
 #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a",  "wally32priv", "wally32periph"]  
 for test in tests32gc:
   tc = TestCase(
@@ -127,7 +127,7 @@ for test in tests32e:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",  "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
+tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",  "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad",
              "arch64priv", "arch64c",  "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
 #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", 
 #             "arch64priv", "arch64c",  "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] 
@@ -141,7 +141,8 @@ if (coverage):  # delete all but 64gc tests when running coverage
        tests64gc.append("arch64d")
        tests64gc.append("arch64zfh")
        tests64gc.append("arch64f_fma")
-       tests64gc.append("arch64d_fma") # *** add arch64zfh_fma when available(see riscv-arch-test pr 367)
+       tests64gc.append("arch64d_fma") 
+       tests64gc.append("arch64zfh_fma")
        tests64gc.append("arch64f_divsqrt")
        tests64gc.append("arch64d_divsqrt")
        tests64gc.append("arch64zfh_divsqrt")

testbench/testbench.sv

@@ -130,7 +130,7 @@ module testbench;
         "arch64zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch64zicboz;
         "arch64zcb":     if (P.ZCB_SUPPORTED)     tests = arch64zcb;
         "arch64zfh":     if (P.ZFH_SUPPORTED)     tests = arch64zfh;
-//        "arch64zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch64zfh_fma; *** not yet in riscv-arch-tst PR367
+        "arch64zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch64zfh_fma; 
         "arch64zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch64zfh_divsqrt;
         "arch64zfaf":    if (P.ZFA_SUPPORTED)     tests = arch64zfaf;
         "arch64zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch64zfad;
@@ -172,7 +172,7 @@ module testbench;
         "arch32zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch32zicboz;
         "arch32zcb":     if (P.ZCB_SUPPORTED)     tests = arch32zcb;
         "arch32zfh":     if (P.ZFH_SUPPORTED)     tests = arch32zfh;
- //       "arch32zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch32zfh_fma; *** not yet in riscv-arch-tst PR367
+        "arch32zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch32zfh_fma; 
         "arch32zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch32zfh_divsqrt;
         "arch32zfaf":    if (P.ZFA_SUPPORTED)     tests = arch32zfaf;
         "arch32zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch32zfad;

testbench/tests.vh

@@ -1126,6 +1126,14 @@ string imperas32f[] = '{
     // "rv64i_m/F/src/fnmsub_b15-01.S"
   };
 
+    string arch64zfh_fma[] = '{
+    `RISCVARCHTEST,
+    //"rv64i_m/F/src/fmadd_b15-01.S",
+    "rv64i_m/Zfh/src/fmsub_b15-01.S"
+    // "rv64i_m/F/src/fnmadd_b15-01.S",
+    // "rv64i_m/F/src/fnmsub_b15-01.S"
+  };
+
   string arch64f_divsqrt[] = '{
     `RISCVARCHTEST,
     "rv64i_m/F/src/fdiv_b20-01.S",
@@ -1393,7 +1401,55 @@ string imperas32f[] = '{
     "rv64i_m/Zfh/src/fsub_b5-01.S",
     "rv64i_m/Zfh/src/fsub_b7-01.S",
     "rv64i_m/Zfh/src/fsub_b8-01.S",
-    "rv64i_m/Zfh/src/fsh-align-01.S"
+    "rv64i_m/Zfh/src/fsh-align-01.S",
+    "rv64i_m/Zfh/src/fmadd_b1-01.S",
+    "rv64i_m/Zfh/src/fmadd_b14-01.S",
+    "rv64i_m/Zfh/src/fmadd_b16-01.S",
+    "rv64i_m/Zfh/src/fmadd_b17-01.S",
+    "rv64i_m/Zfh/src/fmadd_b18-01.S",
+    "rv64i_m/Zfh/src/fmadd_b2-01.S",
+    "rv64i_m/Zfh/src/fmadd_b3-01.S",
+    "rv64i_m/Zfh/src/fmadd_b4-01.S",
+    "rv64i_m/Zfh/src/fmadd_b5-01.S",
+    "rv64i_m/Zfh/src/fmadd_b6-01.S",
+    "rv64i_m/Zfh/src/fmadd_b7-01.S",
+    "rv64i_m/Zfh/src/fmadd_b8-01.S",
+    "rv64i_m/Zfh/src/fmsub_b1-01.S",
+    "rv64i_m/Zfh/src/fmsub_b14-01.S",
+    "rv64i_m/Zfh/src/fmsub_b16-01.S",
+    "rv64i_m/Zfh/src/fmsub_b17-01.S",
+    "rv64i_m/Zfh/src/fmsub_b18-01.S",
+    "rv64i_m/Zfh/src/fmsub_b2-01.S",
+    "rv64i_m/Zfh/src/fmsub_b3-01.S",
+    "rv64i_m/Zfh/src/fmsub_b4-01.S",
+    "rv64i_m/Zfh/src/fmsub_b5-01.S",
+    "rv64i_m/Zfh/src/fmsub_b6-01.S",
+    "rv64i_m/Zfh/src/fmsub_b7-01.S",
+    "rv64i_m/Zfh/src/fmsub_b8-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b1-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b14-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b16-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b17-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b18-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b2-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b3-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b4-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b5-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b6-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b7-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b8-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b1-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b14-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b16-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b17-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b18-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b2-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b3-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b4-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b5-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b6-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b7-01.S",
+    "rv64i_m/Zfh/src/fnmsub_b8-01.S"
     };
 
 
@@ -1975,7 +2031,55 @@ string arch64zbs[] = '{
     "rv32i_m/Zfh/src/fsub_b5-01.S",
     "rv32i_m/Zfh/src/fsub_b7-01.S",
     "rv32i_m/Zfh/src/fsub_b8-01.S",
-    "rv32i_m/Zfh/src/fsh-align-01.S"
+    "rv32i_m/Zfh/src/fsh-align-01.S",
+    "rv32i_m/Zfh/src/fmadd_b1-01.S",
+    "rv32i_m/Zfh/src/fmadd_b14-01.S",
+    "rv32i_m/Zfh/src/fmadd_b16-01.S",
+    "rv32i_m/Zfh/src/fmadd_b17-01.S",
+    "rv32i_m/Zfh/src/fmadd_b18-01.S",
+    "rv32i_m/Zfh/src/fmadd_b2-01.S",
+    "rv32i_m/Zfh/src/fmadd_b3-01.S",
+    "rv32i_m/Zfh/src/fmadd_b4-01.S",
+    "rv32i_m/Zfh/src/fmadd_b5-01.S",
+    "rv32i_m/Zfh/src/fmadd_b6-01.S",
+    "rv32i_m/Zfh/src/fmadd_b7-01.S",
+    "rv32i_m/Zfh/src/fmadd_b8-01.S",
+    "rv32i_m/Zfh/src/fmsub_b1-01.S",
+    "rv32i_m/Zfh/src/fmsub_b14-01.S",
+    "rv32i_m/Zfh/src/fmsub_b16-01.S",
+    "rv32i_m/Zfh/src/fmsub_b17-01.S",
+    "rv32i_m/Zfh/src/fmsub_b18-01.S",
+    "rv32i_m/Zfh/src/fmsub_b2-01.S",
+    "rv32i_m/Zfh/src/fmsub_b3-01.S",
+    "rv32i_m/Zfh/src/fmsub_b4-01.S",
+    "rv32i_m/Zfh/src/fmsub_b5-01.S",
+    "rv32i_m/Zfh/src/fmsub_b6-01.S",
+    "rv32i_m/Zfh/src/fmsub_b7-01.S",
+    "rv32i_m/Zfh/src/fmsub_b8-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b1-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b14-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b16-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b17-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b18-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b2-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b3-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b4-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b5-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b6-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b7-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b8-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b1-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b14-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b16-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b17-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b18-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b2-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b3-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b4-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b5-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b6-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b7-01.S",
+    "rv32i_m/Zfh/src/fnmsub_b8-01.S"
     };
 
   string arch32zfaf[] = '{
@@ -2066,6 +2170,14 @@ string arch64zbs[] = '{
     "rv32i_m/D/src/fnmsub.d_b15-01.S"
   };
 
+string arch32zfh_fma[] = '{
+    `RISCVARCHTEST,
+    //"rv32i_m/D/src/fmadd.d_b15-01.S",
+    //"rv32i_m/D/src/fmsub.d_b15-01.S",
+    // "rv32i_m/D/src/fnmadd.d_b15-01.S",
+    "rv32i_m/Zfh/src/fnmsub.d_b15-01.S"
+  };
+
   string arch32d_divsqrt[] = '{
     `RISCVARCHTEST,
     "rv32i_m/D/src/fdiv.d_b1-01.S",

tests/coverage/fpu.S

@@ -37,6 +37,16 @@ main:
     flw ft0, 0(t0)
     fclass.s t1, ft0
 
+    # zfa instructions (because Zfa tests aren't running yet)
+    fli.d fs0, 16
+    fcvtmod.w.d t0, fs0, rtz
+    fminm.d fs1, fs0, fs0
+    fmaxm.d fs1, fs0, fs0
+    fround.d fs1, fs0
+    froundnx.d fs1, fs0
+    fltq.d t0, fs1, ft0
+    fleq.d t0, fs1, ft0
+
     #Result Sign Test Coverage
     la t0, TestData2
     flw ft0, 0(t0)