Merge pull request #616 from davidharrishmc/dev

Coverage improvements and derivative generation simplification
This commit is contained in:
Rose Thompson 2024-02-04 22:31:02 -06:00 committed by GitHub
commit 0f6c57a032
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GPG Key ID: B5690EEEBB952194
13 changed files with 177 additions and 129 deletions

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@ -76,6 +76,12 @@ foreach my $key (keys %derivs) {
my $configunmod = "$dir/config_unmod.vh";
my $config = "$dir/config.vh";
my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh";
if (! -e $base) {
$base = "$ENV{WALLY}/config/deriv/$basederiv{$key}/config.vh";
if (! -e $base) {
die("Unable to find base config $base for $key\n");
}
}
system("cp $base $configunmod");
open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!";
open(my $fh, '>>', $config) or die "Could not open file '$config' $!";

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@ -46,7 +46,7 @@ UART_PRESCALE 32'd0
PLIC_NUM_SRC 32'd53
# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM)
deriv fpga rv64gc buildroot
deriv fpga buildroot
BOOTROM_PRELOAD 1
UNCORE_RAM_BASE 64'h2000
UNCORE_RAM_RANGE 64'hFFF
@ -71,7 +71,7 @@ BTB_SIZE 32'd5
# The other syn configurations have the same trimming
deriv syn_rv32i rv32i syn_rv32e
deriv syn_rv32imc rv32imc syn_rv32e
deriv syn_rv32gc rv32gc syn_rv32e
deriv syn_rv32gc syn_rv32e
deriv syn_rv64i rv64i syn_rv32e
deriv syn_rv64gc rv64gc syn_rv32e
@ -84,34 +84,34 @@ USE_SRAM 1
# The other syn configurations have the same trimming
deriv syn_sram_rv32i rv32i syn_sram_rv32e
deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
deriv syn_sram_rv32gc syn_sram_rv32e
deriv syn_sram_rv64i rv64i syn_sram_rv32e
deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
# The following syn configurations gradually turn off features
deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
deriv syn_pmp0_rv64gc syn_rv64gc
PMP_ENTRIES 32'd0
deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc
PMP_ENTRIES 32'd0
deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
deriv syn_noPriv_rv64gc syn_pmp0_rv64gc
ZICSR_SUPPORTED 0
deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc
deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc
ZICSR_SUPPORTED 0
deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc
deriv syn_noFPU_rv64gc syn_noPriv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc
deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc
deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc
deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc
deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20)
deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc
deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20)
# Divider variants to check logical correctness
@ -147,22 +147,22 @@ RADIX 32'd4
DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc
deriv div_2_1i_rv32gc div_2_1_rv32gc
IDIV_ON_FPU 1
deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc
deriv div_2_2i_rv32gc div_2_2_rv32gc
IDIV_ON_FPU 1
deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc
deriv div_2_4i_rv32gc div_2_4_rv32gc
IDIV_ON_FPU 1
deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc
deriv div_4_1i_rv32gc div_4_1_rv32gc
IDIV_ON_FPU 1
deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc
deriv div_4_2i_rv32gc div_4_2_rv32gc
IDIV_ON_FPU 1
deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc
deriv div_4_4i_rv32gc div_4_4_rv32gc
IDIV_ON_FPU 1
deriv div_2_1_rv64gc rv64gc
@ -195,22 +195,22 @@ RADIX 32'd4
DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc
deriv div_2_1i_rv64gc div_2_1_rv64gc
IDIV_ON_FPU 1
deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc
deriv div_2_2i_rv64gc div_2_2_rv64gc
IDIV_ON_FPU 1
deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc
deriv div_2_4i_rv64gc div_2_4_rv64gc
IDIV_ON_FPU 1
deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc
deriv div_4_1i_rv64gc div_4_1_rv64gc
IDIV_ON_FPU 1
deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc
deriv div_4_2i_rv64gc div_4_2_rv64gc
IDIV_ON_FPU 1
deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc
deriv div_4_4i_rv64gc div_4_4_rv64gc
IDIV_ON_FPU 1
# RAM latency and Burst mode for bus stress testing
@ -255,22 +255,22 @@ BPRED_SIZE 32'd14
deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
BPRED_SIZE 32'd16
deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
deriv bpred_TWOBIT_6_16_10_1_rv32gc bpred_GSHARE_6_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
deriv bpred_TWOBIT_8_16_10_1_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
deriv bpred_TWOBIT_10_16_10_1_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
deriv bpred_TWOBIT_12_16_10_1_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
deriv bpred_TWOBIT_14_16_10_1_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
deriv bpred_TWOBIT_16_16_10_1_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
BPRED_TYPE `BP_TWOBIT
deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
@ -309,73 +309,73 @@ BTB_SIZE 32'd16
deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
deriv bpred_GSHARE_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
deriv bpred_GSHARE_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
deriv bpred_GSHARE_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
deriv bpred_GSHARE_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc
deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc
deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc
deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc
deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc
deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc
deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc
deriv bpred_GSHARE_10_3_10_0_rv32gc bpred_GSHARE_10_3_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc
deriv bpred_GSHARE_10_4_10_0_rv32gc bpred_GSHARE_10_4_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc
deriv bpred_GSHARE_10_6_10_0_rv32gc bpred_GSHARE_10_6_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_10_10_0_rv32gc rv32gc bpred_GSHARE_10_10_10_1_rv32gc
deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_6_0_rv32gc rv32gc bpred_GSHARE_10_16_6_1_rv32gc
deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_8_0_rv32gc rv32gc bpred_GSHARE_10_16_8_1_rv32gc
deriv bpred_GSHARE_10_16_8_0_rv32gc bpred_GSHARE_10_16_8_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_12_0_rv32gc rv32gc bpred_GSHARE_10_16_12_1_rv32gc
deriv bpred_GSHARE_10_16_12_0_rv32gc bpred_GSHARE_10_16_12_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_14_0_rv32gc rv32gc bpred_GSHARE_10_16_14_1_rv32gc
deriv bpred_GSHARE_10_16_14_0_rv32gc bpred_GSHARE_10_16_14_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_16_0_rv32gc rv32gc bpred_GSHARE_10_16_16_1_rv32gc
deriv bpred_GSHARE_10_16_16_0_rv32gc bpred_GSHARE_10_16_16_1_rv32gc
INSTR_CLASS_PRED 0
# Cache configurations
@ -424,23 +424,23 @@ ICACHE_NUMWAYS 32'd1
ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 32'd512
deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
deriv way_2_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd1
ICACHE_NUMWAYS 32'd1
deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
deriv way_4_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd4
ICACHE_NUMWAYS 32'd4
deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
deriv way_8_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd8
ICACHE_NUMWAYS 32'd8
deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
deriv way_4_2048_512_rv32gc way_4_4096_512_rv32gc
DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 32'd2048
deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
deriv way_4_4096_256_rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 32'd256
@ -452,27 +452,27 @@ ICACHE_NUMWAYS 32'd1
ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 32'd512
deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
deriv way_2_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 32'd1
ICACHE_NUMWAYS 32'd1
deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
deriv way_4_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 32'd4
ICACHE_NUMWAYS 32'd4
deriv way_8_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
deriv way_8_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 32'd8
ICACHE_NUMWAYS 32'd8
deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
deriv way_4_2048_512_rv64gc way_4_4096_512_rv64gc
DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 32'd2048
deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
deriv way_4_4096_256_rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 32'd256
deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
deriv way_4_4096_1024_rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 32'd1024
ICACHE_LINELENINBITS 32'd1024
@ -552,32 +552,32 @@ ZFH_SUPPORTED 1
# IEEE compatible variants for TestFloat
deriv f_ieee_rv32gc rv32gc f_rv32gc
deriv f_ieee_rv32gc f_rv32gc
IEEE754 1
deriv fh_ieee_v32gc rv32gc fh_rv32gc
deriv fh_ieee_v32gc fh_rv32gc
IEEE754 1
deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc
deriv fdh_ieee_rv32gc fdh_rv32gc
IEEE754 1
deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc
deriv fdq_ieee_rv32gc fdq_rv32gc
IEEE754 1
deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc
deriv fdqh_ieee_rv32gc fdqh_rv32gc
IEEE754 1
deriv f_ieee_rv64gc rv64gc f_rv64gc
deriv f_ieee_rv64gc f_rv64gc
IEEE754 1
deriv fh_ieee_rv64gc rv64gc fh_rv64gc
deriv fh_ieee_rv64gc fh_rv64gc
IEEE754 1
deriv fd_ieee_rv64gc rv64gc fd_rv64gc
deriv fd_ieee_rv64gc fd_rv64gc
IEEE754 1
deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc
deriv fdq_ieee_rv64gc fdq_rv64gc
IEEE754 1
deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc
deriv fdqh_ieee_rv64gc fdqh_rv64gc
IEEE754 1

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@ -58,11 +58,12 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineN
# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
# Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY
# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
# exclude branch/condition coverage: LineDirty if statement
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
# exclude the unreachable logic
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"]
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"]
@ -81,7 +82,9 @@ set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdir
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
# cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
@ -100,6 +103,26 @@ for {set i 0} {$i < $numcacheways} {incr i} {
# No dirty ways in read-only I$
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
}
# I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
## D$ Exclusions.
# InvalidateCache is I$ only:
@ -117,10 +140,10 @@ for {set i 0} {$i < $numcacheways} {incr i} {
# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -fecexprrow 6
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
}
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
####################
# Unused / illegal peripheral accesses
@ -170,22 +193,15 @@ set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
# set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"]
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec
# No DTIM or IROM
coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
####################
# Unused access types due to sharing IFU and LSU logic
####################
@ -228,6 +244,10 @@ set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
@ -320,7 +340,7 @@ coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item
set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm Atomic"]
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
@ -338,15 +358,15 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefs
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
# all of these HEADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls.
# all of these HREADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls.
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
@ -362,6 +382,14 @@ set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREAD
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
# these transitions will not happen
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE
# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
# This is a blunt instrument; perhaps there is a more graceful exclusion
coverage exclude -srcfile priorityonehot.sv
@ -370,6 +398,13 @@ coverage exclude -srcfile priorityonehot.sv
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
####################
# Privileged
####################
# Instruction Misaligned never asserted because compresssed instructions are accepted
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ../src/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
####################
# EBU
####################

View File

@ -127,7 +127,7 @@ for test in tests32e:
grepstr="All tests ran without failures")
configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
@ -135,7 +135,7 @@ if (coverage): # delete all but 64gc tests when running coverage
configs = []
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
"arch64zba", "arch64zbb", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
if (fp):
tests64gc.append("arch64f")
tests64gc.append("arch64d")

View File

@ -143,7 +143,7 @@ module cacheLRU
// This is a two port memory.
// Every cycle must read from CacheSetData and each load/store must write the new LRU.
always_ff @(posedge clk) begin
if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0;
if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize
if(CacheEn) begin
if(ClearValid & ~FlushStage)
LRUMemory[PAdr] <= '0;

10
src/cache/cachefsm.sv vendored
View File

@ -117,12 +117,11 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
NextState = STATE_READY;
case (CurrState) // exclusion-tag: icache state-case
STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; // exclusion-tag: icache FLUSHStatement
else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else if((AnyMiss | CMOWriteback) & ~READ_ONLY_CACHE) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else if(CacheBusAck) NextState = STATE_READY;
else NextState = STATE_FETCH;
STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
@ -158,7 +157,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
(CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]);
assign ClearValid = (CurrState == STATE_READY & CMOpM[0]) |
(CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck);
// coverage off -item e 1 -fecexprrow 8
assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
(CurrState == STATE_WRITEBACK & CMOpM[3] & CacheBusAck);
@ -190,8 +188,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
(CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOpM));
logic LoadMiss;
//assign StoreMiss = (CacheRW[0]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
assign LoadMiss = (CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
assign CacheBusRW[0] = (CurrState == STATE_READY & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW
@ -204,7 +200,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
(CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) |
resetDelay;
assign SelAdrTag = (CurrState == STATE_READY & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
assign SelAdrTag = (CurrState == STATE_READY & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrTag // changes if store delay hazard removed
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) |

View File

@ -53,7 +53,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
output logic HitWay, // This way hits
output logic ValidWay, // This way is valid
output logic HitDirtyWay, // The hit way is dirty
output logic HitDirtyWay, // The hit way is dirty
output logic DirtyWay , // The selected way is dirty
output logic [TAGLEN-1:0] TagWay); // This way's tag if valid

View File

@ -79,7 +79,7 @@ module buscachefsm #(
logic CacheAccess;
logic BusWrite;
assign BusWrite = CacheBusRW[0] | BusCMOZero;
assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE;
always_ff @(posedge HCLK)
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
@ -87,28 +87,28 @@ module buscachefsm #(
always_comb begin
case(CurrState)
ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
else if (HREADY & BusWrite & ~READ_ONLY_CACHE) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADYread
else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
DATA_PHASE: if(HREADY & BusAtomic & ~READ_ONLY_CACHE) NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
else if(HREADY & ~BusAtomic) NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
else NextState = DATA_PHASE;
ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE;
else NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm Atomic
ATOMIC_PHASE: if(HREADY) NextState = MEM3;
else NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait
ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicReadData
else NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm AtomicElse
ATOMIC_PHASE: if(HREADY) NextState = MEM3; // exclusion-tag: buscachefsm AtomicPhase
else NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait
MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm FetchWriteback
else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm FetchWait
else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
else NextState = CACHE_FETCH;
CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADY4
else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3; // exclusion-tag: buscachefsm HREADY5
else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; // exclusion-tag: buscachefsm HREADY6
else NextState = CACHE_WRITEBACK;
else NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback2
default: NextState = ADR_PHASE;
endcase
end
@ -139,12 +139,12 @@ module buscachefsm #(
// AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) |
(CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
(CurrState == ATOMIC_READ_DATA_PHASE) |
(CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
(CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
(CurrState == CACHE_WRITEBACK & |BeatCount);
assign HWRITE = (((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
(CurrState == CACHE_WRITEBACK & |BeatCount)) & ~READ_ONLY_CACHE;
assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
always_comb begin

View File

@ -142,7 +142,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
always_comb
if (BadNaNBox & Fmt == P.FMT1)
PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
else if (BadNaNBox & Fmt == P.FMT2)
else if (BadNaNBox) // Fmt == P.FMT2
PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
else
PostBox = In;

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@ -27,9 +27,8 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $fatal(1, "Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");

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@ -180,7 +180,7 @@ module testbench;
end
if (tests.size() == 0) begin
$display("TEST %s not supported in this configuration", TEST);
$stop;
$finish;
end
end // initial begin
@ -300,7 +300,7 @@ module testbench;
if (TEST == "coremark")
if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done.");
$stop;
$finish;
end
if(Validate) begin
if (TEST == "embench") begin
@ -337,7 +337,7 @@ module testbench;
if (test == tests.size()) begin
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors);
$stop;
$finish;
end
end
end
@ -601,7 +601,7 @@ module testbench;
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
$stop;
$finish;
end
end
if (errors) $display("%s failed with %d errors. :(", TestName, errors);

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@ -109,6 +109,12 @@ main:
# fcvt.w.q a0, ft0
# fcvt.q.d ft3, ft0
# half-precision NaN boxing
la t0, TestData3
fld ft2, 0(t0) // bad NaN-boxed number
fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing
fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing
// fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives)
// This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes.
li t0, 0x3F812345 # random value slightly bigger than 1
@ -206,4 +212,6 @@ TestData2:
.int 0xbf800000 #FP -1.0
.int 0x7fa00000 #SNaN
.int 0x3fffffff #OverFlow Test
TestData3:
.dword 0xABCD543212345678 # NaN box test
DivTestData:

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@ -206,6 +206,10 @@ ConcurrentICacheMissDTLBMiss:
# change back to default trap handler after checking everything that might cause an instruction page fault
jal changetodefaulthandler
# uncachable AMO access
li t0, 0x80401000 # PBMT sets as uncachable
amoadd.w t0, t0, 0(t0)
# exercise CBOM instructions with various permissions
li t0, 0x80800000
cbo.zero (t0)
@ -457,8 +461,8 @@ SpecialPage:
# Leaf page table at 0x80014000 with PBMT pages
.align 12
#80400000
.8byte 0x60000000200020CF # reserved entry
.8byte 0x40000000201000CF # non-cache non-idempotent
.8byte 0x60000000200020CF # reserved entry VA 80400000
.8byte 0x40000000201000CF # non-cache non-idempotent VA 80401000
# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
.align 12