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Added M suffix in atomic
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@ -34,7 +34,7 @@ module amoalu (
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input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
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input logic [6:0] LSUFunct7M, // ALU Operation
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input logic [2:0] LSUFunct3M, // Memoy access width
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output logic [`XLEN-1:0] AMOResult // ALU output
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output logic [`XLEN-1:0] AMOResultM // ALU output
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);
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logic [`XLEN-1:0] a, b, y;
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@ -60,17 +60,17 @@ module amoalu (
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if (`XLEN == 32) begin:sext
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assign a = ReadDataM;
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assign b = IHWriteDataM;
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assign AMOResult = y;
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assign AMOResultM = y;
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end else begin:sext // `XLEN = 64
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always_comb
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if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
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a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
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b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
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AMOResult = {{32{y[31]}}, y[31:0]};
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AMOResultM = {{32{y[31]}}, y[31:0]};
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end else begin
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a = ReadDataM;
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b = IHWriteDataM;
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AMOResult = y;
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AMOResultM = y;
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end
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end
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endmodule
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@ -38,7 +38,7 @@ module atomic (
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input logic [`PA_BITS-1:0] PAdrM, // Physical memory address
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input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
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input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
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input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
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input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
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input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
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input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
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output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
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@ -46,12 +46,12 @@ module atomic (
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output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
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);
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logic [`XLEN-1:0] AMOResult;
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logic [`XLEN-1:0] AMOResultM;
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logic MemReadM;
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amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult);
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amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
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mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
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mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
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lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
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