diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv
index eda3576be..d2670449a 100644
--- a/src/lsu/amoalu.sv
+++ b/src/lsu/amoalu.sv
@@ -34,7 +34,7 @@ module amoalu (
   input  logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
   input  logic [6:0]       LSUFunct7M,   // ALU Operation
   input  logic [2:0]       LSUFunct3M,   // Memoy access width
-  output logic [`XLEN-1:0] AMOResult     // ALU output
+  output logic [`XLEN-1:0] AMOResultM    // ALU output
 );
 
   logic [`XLEN-1:0] a, b, y;
@@ -60,17 +60,17 @@ module amoalu (
   if (`XLEN == 32) begin:sext
     assign a = ReadDataM;
     assign b = IHWriteDataM;
-    assign AMOResult = y;
+    assign AMOResultM = y;
   end else begin:sext // `XLEN = 64
     always_comb 
       if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
         a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
         b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
-        AMOResult = {{32{y[31]}}, y[31:0]};
+        AMOResultM = {{32{y[31]}}, y[31:0]};
       end else begin
         a = ReadDataM;
         b = IHWriteDataM;
-        AMOResult = y;
+        AMOResultM = y;
       end
   end
 endmodule
diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
index fc9ede119..d33e85fe5 100644
--- a/src/lsu/atomic.sv
+++ b/src/lsu/atomic.sv
@@ -38,7 +38,7 @@ module atomic (
   input logic [`PA_BITS-1:0] PAdrM,          // Physical memory address
   input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
   input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
-  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
+  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
   input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
   input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
   output logic [`XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
@@ -46,12 +46,12 @@ module atomic (
   output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
 );
 
-  logic [`XLEN-1:0]          AMOResult;
+  logic [`XLEN-1:0]          AMOResultM;
   logic                      MemReadM;
 
-  amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult);
+  amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
 
-  mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
+  mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
 
   lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);