Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 10:15:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added M suffix in atomic

Browse Source
This commit is contained in:
David Harris 2023-04-24 12:19:56 -07:00
parent e73922d34d
commit ee6a3f49f0
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/lsu/amoalu.sv
View File

@ -34,7 +34,7 @@ module amoalu (
input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
input logic [6:0] LSUFunct7M, // ALU Operation input logic [6:0] LSUFunct7M, // ALU Operation
input logic [2:0] LSUFunct3M, // Memoy access width input logic [2:0] LSUFunct3M, // Memoy access width
output logic [`XLEN-1:0] AMOResult // ALU output output logic [`XLEN-1:0] AMOResultM // ALU output
); );
logic [`XLEN-1:0] a, b, y; logic [`XLEN-1:0] a, b, y;
@ -60,17 +60,17 @@ module amoalu (
if (`XLEN == 32) begin:sext if (`XLEN == 32) begin:sext
assign a = ReadDataM; assign a = ReadDataM;
assign b = IHWriteDataM; assign b = IHWriteDataM;
assign AMOResult = y; assign AMOResultM = y;
end else begin:sext // `XLEN = 64 end else begin:sext // `XLEN = 64
always_comb always_comb
if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
a = {{32{ReadDataM[31]}}, ReadDataM[31:0]}; a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]}; b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
AMOResult = {{32{y[31]}}, y[31:0]}; AMOResultM = {{32{y[31]}}, y[31:0]};
end else begin end else begin
a = ReadDataM; a = ReadDataM;
b = IHWriteDataM; b = IHWriteDataM;
AMOResult = y; AMOResultM = y;
end end
end end
endmodule endmodule

8
src/lsu/atomic.sv
View File

@ -38,7 +38,7 @@ module atomic (
input logic [`PA_BITS-1:0] PAdrM, // Physical memory address input logic [`PA_BITS-1:0] PAdrM, // Physical memory address
input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
@ -46,12 +46,12 @@ module atomic (
output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
); );
logic [`XLEN-1:0] AMOResult; logic [`XLEN-1:0] AMOResultM;
logic MemReadM; logic MemReadM;
amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult); amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM); mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);