From ecce1e62ee472dbad732b6d65ddcf91cf719a295 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 14 Dec 2021 13:05:32 -0800
Subject: [PATCH] changed ideal memory to MEM_DTIM and MEM_ITIM

---
 wally-pipelined/config/buildroot/wally-config.vh     | 5 +++--
 wally-pipelined/config/busybear/wally-config.vh      | 3 ++-
 wally-pipelined/config/coremark/wally-config.vh      | 8 ++++----
 wally-pipelined/config/coremark_bare/wally-config.vh | 6 +++---
 wally-pipelined/config/fpga/wally-config.vh          | 5 +++--
 wally-pipelined/config/rv32gc/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv32ic/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv64BP/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv64gc/wally-config.vh        | 7 ++++---
 wally-pipelined/config/rv64ic/wally-config.vh        | 5 +++--
 wally-pipelined/regression/sim-wally                 | 2 +-
 11 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index d2b532b25..9ec59f627 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index b248c58a5..e969f1b08 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -48,8 +48,9 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index ceb546ff6..b02a4a7f3 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -43,16 +43,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
-`define MEM_VIRTMEM 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define MEM_VIRTMEM 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index 0adca26be..ddde51f03 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -44,16 +44,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/fpga/wally-config.vh b/wally-pipelined/config/fpga/wally-config.vh
index 872045439..909125f87 100644
--- a/wally-pipelined/config/fpga/wally-config.vh
+++ b/wally-pipelined/config/fpga/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv32gc/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh
index 006981201..7f4b10648 100644
--- a/wally-pipelined/config/rv32gc/wally-config.vh
+++ b/wally-pipelined/config/rv32gc/wally-config.vh
@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index b48417739..1c62f513a 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh
index 246901583..8105f1a4f 100644
--- a/wally-pipelined/config/rv64BP/wally-config.vh
+++ b/wally-pipelined/config/rv64BP/wally-config.vh
@@ -48,11 +48,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64gc/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh
index d8378ab96..b45631323 100644
--- a/wally-pipelined/config/rv64gc/wally-config.vh
+++ b/wally-pipelined/config/rv64gc/wally-config.vh
@@ -43,15 +43,16 @@
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
 
-// Microarchitectural Features
+/// Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index afd2e8d61..31fcc0f2c 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index d3071bd15..422fb77e9 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64g arch64i"
+vsim -do "do wally-pipelined.do rv64gc arch64i"