From ebef47b1c92498913a47b0e0a01d3abc114829a1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 24 Oct 2021 21:21:49 -0500
Subject: [PATCH] Modified the cache's sram model so if it used to synthesize
 flip flops it terminates the read critical path at the address's input rather
 than the output read data.

---
 wally-pipelined/src/cache/sram1rw.sv | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/cache/sram1rw.sv b/wally-pipelined/src/cache/sram1rw.sv
index d2b4b8470..835e7061f 100644
--- a/wally-pipelined/src/cache/sram1rw.sv
+++ b/wally-pipelined/src/cache/sram1rw.sv
@@ -14,13 +14,19 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
 );
 
     logic [WIDTH-1:0][DEPTH-1:0] StoredData;
+    logic [$clog2(WIDTH)-1:0] 	 AddrD;
+  
 
     always_ff @(posedge clk) begin
-        ReadData <= StoredData[Addr];
+      AddrD <= Addr;
         if (WriteEnable) begin
             StoredData[Addr] <= #1 WriteData;
         end
     end
+
+      
+  assign ReadData = StoredData[AddrD];
+  
 endmodule
 
 /* verilator lint_on ASSIGNDLY */