Updated fpga test bench.

Solved read delay cache bug.  Introduced during cache optimizations.

pipelined/src/cache/cache.sv

@@ -50,8 +50,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   output logic                  CacheAccess,
    // lsu control
   input logic                   IgnoreRequestTLB,
-  input logic                   DCacheTrapM, 
+  input logic                   TrapM, 
-  input logic                   ICacheTrapM,
   input logic                   Cacheable,
    // Bus fsm interface
   output logic                  CacheFetchLine,
@@ -214,7 +213,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   assign CacheRW = Cacheable ? RW : 2'b00;
   assign CacheAtomic = Cacheable ? Atomic : 2'b00;
   cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, 
-		.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .DCacheTrapM, .ICacheTrapM,
+		.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM,
  		.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, 
 		.CacheMiss, .CacheAccess, .SelAdr, 
 		.ClearValid, .ClearDirty, .SetDirty,

pipelined/src/cache/cachefsm.sv

@@ -140,9 +140,10 @@ module cachefsm
       else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
                             else                               NextState = STATE_MISS_FETCH_WDV;
       //STATE_MISS_WRITE_CACHE_LINE:                             NextState = STATE_READY;
-      STATE_MISS_WRITE_CACHE_LINE: if(~(AMO | CacheRW[0]))    NextState = STATE_MISS_READ_DELAY;
+      STATE_MISS_WRITE_CACHE_LINE: if(~(AMO | CacheRW[0]))     NextState = STATE_MISS_READ_DELAY;
                                    else                        NextState = STATE_READY;
-      STATE_MISS_READ_DELAY:                                   NextState = STATE_READY;
+      STATE_MISS_READ_DELAY: if(CPUBusy)                       NextState = STATE_MISS_READ_DELAY;
+                             else                              NextState = STATE_READY;
       STATE_MISS_EVICT_DIRTY: if(CacheBusAck)                  NextState = STATE_MISS_WRITE_CACHE_LINE;
                               else                             NextState = STATE_MISS_EVICT_DIRTY;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.

pipelined/src/ifu/ifu.sv

@@ -223,7 +223,7 @@ module ifu (
       cache #(.LINELEN(`ICACHE_LINELENINBITS),
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
-      icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .ICacheTrapM(TrapM), .DCacheTrapM('0),
+      icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM,
              .LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
              .CacheFetchLine(ICacheFetchLine),

pipelined/src/lsu/lsu.sv

@@ -245,7 +245,7 @@ module lsu (
         .ByteMask(FinalByteMaskM), .WordCount,
         .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
-        .IgnoreRequestTLB, .DCacheTrapM(TrapM), .ICacheTrapM(1'b0), .CacheCommitted(DCacheCommittedM), 
+        .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), 
         .LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine), 
         .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));

pipelined/testbench/testbench-fpga.sv

@@ -136,14 +136,15 @@ logic [3:0] dummy;
       if (TEST == "coremark") 
 
       // read test vectors into memory
-      pathname = tvpaths[tests[0].atoi()];
+      //pathname = tvpaths[tests[0].atoi()];
+        pathname = "../../tests/testsBP/fpga-test-sdc/bin/";
 /*      if (tests[0] == `IMPERASTEST)
         pathname = tvpaths[0];
       else pathname = tvpaths[1]; */
-      memfilename = {pathname, tests[test], ".elf.memfile"};
+      memfilename = "../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile";
       romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
       sdcfilename = {"../testbench/sdc/ramdisk2.hex"};      
-      //$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM);
+      $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM);
       $readmemh(sdcfilename, sdcard.FLASHmem);
 
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
@@ -287,9 +288,19 @@ logic [3:0] dummy;
 
   // initialize the branch predictor
   if (`BPRED_ENABLED == 1)
-    initial begin
+    begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      genvar adrindex;
-      $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+      
+      // Initializing all zeroes into the branch predictor memory.
+      for(adrindex = 0; adrindex < 1024; adrindex++) begin
+        initial begin 
+        force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+        force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        #1;
+        release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+        release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+        end
+      end
     end
 endmodule