diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 00e11bdb6..fd71e6526 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -50,8 +50,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE output logic CacheAccess, // lsu control input logic IgnoreRequestTLB, - input logic DCacheTrapM, - input logic ICacheTrapM, + input logic TrapM, input logic Cacheable, // Bus fsm interface output logic CacheFetchLine, @@ -214,7 +213,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign CacheRW = Cacheable ? RW : 2'b00; assign CacheAtomic = Cacheable ? Atomic : 2'b00; cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, - .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .DCacheTrapM, .ICacheTrapM, + .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 537be6ebb..4cf17db99 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -140,9 +140,10 @@ module cachefsm else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_FETCH_WDV; //STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; - STATE_MISS_WRITE_CACHE_LINE: if(~(AMO | CacheRW[0])) NextState = STATE_MISS_READ_DELAY; + STATE_MISS_WRITE_CACHE_LINE: if(~(AMO | CacheRW[0])) NextState = STATE_MISS_READ_DELAY; else NextState = STATE_READY; - STATE_MISS_READ_DELAY: NextState = STATE_READY; + STATE_MISS_READ_DELAY: if(CPUBusy) NextState = STATE_MISS_READ_DELAY; + else NextState = STATE_READY; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index b009bcb4b..b8e636c5f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -223,7 +223,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .ICacheTrapM(TrapM), .DCacheTrapM('0), + icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM, .LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 95e9c8021..b278306a1 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -245,7 +245,7 @@ module lsu ( .ByteMask(FinalByteMaskM), .WordCount, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), - .IgnoreRequestTLB, .DCacheTrapM(TrapM), .ICacheTrapM(1'b0), .CacheCommitted(DCacheCommittedM), + .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); diff --git a/pipelined/testbench/testbench-fpga.sv b/pipelined/testbench/testbench-fpga.sv index c815d8a02..2a161d97e 100644 --- a/pipelined/testbench/testbench-fpga.sv +++ b/pipelined/testbench/testbench-fpga.sv @@ -136,14 +136,15 @@ logic [3:0] dummy; if (TEST == "coremark") // read test vectors into memory - pathname = tvpaths[tests[0].atoi()]; + //pathname = tvpaths[tests[0].atoi()]; + pathname = "../../tests/testsBP/fpga-test-sdc/bin/"; /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ - memfilename = {pathname, tests[test], ".elf.memfile"}; + memfilename = "../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"; romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - //$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM); + $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM); $readmemh(sdcfilename, sdcard.FLASHmem); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; @@ -286,11 +287,21 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) - initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - end + if (`BPRED_ENABLED == 1) + begin + genvar adrindex; + + // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 1024; adrindex++) begin + initial begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + #1; + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + end + end endmodule module riscvassertions;