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Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.

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Rose Thompson 2024-03-05 10:33:47 -06:00 committed by GitHub
parent 1a0097f6e7
commit e8e0538f6c
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1 changed files with 5 additions and 7 deletions
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12
src/cache/cacheLRU.sv vendored
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@ -143,16 +143,14 @@ module cacheLRU
// This is a two port memory. // This is a two port memory.
// Every cycle must read from CacheSetData and each load/store must write the new LRU. // Every cycle must read from CacheSetData and each load/store must write the new LRU.
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
if(CacheEn) begin if(CacheEn) begin
if(ClearValid & ~FlushStage) if(LRUWriteEn)
LRUMemory[PAdr] = '0; LRUMemory[PAdr] <= NextLRU;
else if(LRUWriteEn)
LRUMemory[PAdr] = NextLRU;
if(LRUWriteEn & (PAdr == CacheSetTag)) if(LRUWriteEn & (PAdr == CacheSetTag))
CurrLRU = NextLRU; CurrLRU <= NextLRU;
else else
CurrLRU = LRUMemory[CacheSetTag]; CurrLRU <= LRUMemory[CacheSetTag];
end end
end end