diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 1b803f5d3..26bdca887 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -143,16 +143,14 @@ module cacheLRU
   // This is a two port memory.
   // Every cycle must read from CacheSetData and each load/store must write the new LRU.
   always_ff @(posedge clk) begin
-    if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0;
+    if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
     if(CacheEn) begin
-      if(ClearValid & ~FlushStage)
-        LRUMemory[PAdr] = '0;
-      else if(LRUWriteEn)
-        LRUMemory[PAdr] = NextLRU;
+      if(LRUWriteEn)
+        LRUMemory[PAdr] <= NextLRU;
       if(LRUWriteEn & (PAdr == CacheSetTag))
-        CurrLRU = NextLRU;
+        CurrLRU <= NextLRU;
       else 
-        CurrLRU = LRUMemory[CacheSetTag];
+        CurrLRU <= LRUMemory[CacheSetTag];
     end
   end