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Fix fcvt.lu.s bug and lint issue in packoutput

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This commit is contained in:
David Harris 2024-05-12 11:31:27 -07:00
parent 380d88fc68
commit e87a269f59
2 changed files with 14 additions and 12 deletions
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10
config/shared/config-shared.vh
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@ -119,14 +119,14 @@ localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75 // RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75
// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89 // RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89
// RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162 // RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162
// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing on // *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing for fcvt.lu.s
// with CVTLEN+NF+1. Changing to CVTLEN+NF+1+2 fixes failures // with CVTLEN+NF+1. Changing to CVTLEN+NF+1+2 fixes failures
// This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64 // This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64
// because NORMSHIFTSZ becomes limited by convert rather than divider // because NORMSHIFTSZ becomes limited by convert rather than divider
// Figure out why extra two bits are needed for convert (and only in testbench_fp, not Wally) // The two extra bits are necessary because shiftcorrection dropped them for fcvt.
// Might be a testbench_fp issue // May be possible to remove these two bits by modifying shiftcorrection
//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8)); localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8));
localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8)); //localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8));
localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ) localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)
localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop leading 2 integer bits localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop leading 2 integer bits

16
src/fpu/packoutput.sv
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@ -48,11 +48,8 @@ module packoutput import cvw::*; #(parameter cvw_t P) (
if (P.FPSIZES == 1) begin if (P.FPSIZES == 1) begin
assign Packed = Unpacked; assign Packed = Unpacked;
end else if (P.FPSIZES == 2) begin end else if (P.FPSIZES == 2) begin
int NF = P.NF; always_comb begin
int NE1 = P.NE1; {Exp1, Fract1} = '0; // default if not used, to prevent latch
int top = P.NF + P.NE1-2;
int bot = P.NF - P.NF1;
always_comb
case (Fmt) case (Fmt)
1'b1: Packed = Unpacked; 1'b1: Packed = Unpacked;
1'b0: begin 1'b0: begin
@ -61,8 +58,10 @@ module packoutput import cvw::*; #(parameter cvw_t P) (
Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1};
end end
endcase endcase
end
end else if (P.FPSIZES == 3) begin end else if (P.FPSIZES == 3) begin
always_comb always_comb begin
{Exp1, Fract1, Exp2, Fract2} = '0; // default if not used, to prevent latch
case (Fmt) case (Fmt)
P.FMT: Packed = Unpacked; P.FMT: Packed = Unpacked;
P.FMT1: begin P.FMT1: begin
@ -77,8 +76,10 @@ module packoutput import cvw::*; #(parameter cvw_t P) (
end end
default: Packed = 'x; default: Packed = 'x;
endcase endcase
end
end else if (P.FPSIZES == 4) begin end else if (P.FPSIZES == 4) begin
always_comb always_comb begin
{Exp1, Fract1, Exp2, Fract2, Exp3, Fract3} = '0; // default if not used, to prevent latch
case (Fmt) case (Fmt)
2'h3: Packed = Unpacked; // Quad 2'h3: Packed = Unpacked; // Quad
2'h1: begin // double 2'h1: begin // double
@ -98,4 +99,5 @@ module packoutput import cvw::*; #(parameter cvw_t P) (
end end
endcase endcase
end end
end
endmodule endmodule