diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index b9135d1b0..2401cada2 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -119,14 +119,14 @@ localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
 // RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75
 // RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89
 // RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162
-// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing on  
+// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing for fcvt.lu.s
 //     with CVTLEN+NF+1.  Changing to CVTLEN+NF+1+2 fixes failures
 //     This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64
 //     because NORMSHIFTSZ becomes limited by convert rather than divider
-//     Figure out why extra two bits are needed for convert (and only in testbench_fp, not Wally)
-//     Might be a testbench_fp issue
-//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8));
-localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8));
+//     The two extra bits are necessary because shiftcorrection dropped them for fcvt.
+//     May be possible to remove these two bits by modifying shiftcorrection
+localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8));
+//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8));
 
 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
 localparam CORRSHIFTSZ = NORMSHIFTSZ-2;                             // Drop leading 2 integer bits
diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv
index 332c0ed52..c9a500700 100644
--- a/src/fpu/packoutput.sv
+++ b/src/fpu/packoutput.sv
@@ -48,11 +48,8 @@ module packoutput import cvw::*;  #(parameter cvw_t P) (
   if (P.FPSIZES == 1) begin
     assign Packed = Unpacked;
   end else if (P.FPSIZES == 2) begin
-    int NF = P.NF;
-    int NE1 = P.NE1;
-    int top = P.NF + P.NE1-2;
-    int bot = P.NF - P.NF1;
-    always_comb
+    always_comb begin
+      {Exp1, Fract1} = '0; // default if not used, to prevent latch
       case (Fmt)
         1'b1: Packed = Unpacked;
         1'b0: begin
@@ -61,8 +58,10 @@ module packoutput import cvw::*;  #(parameter cvw_t P) (
                 Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
               end
       endcase
+    end
   end else if (P.FPSIZES == 3) begin
-    always_comb
+    always_comb begin
+      {Exp1, Fract1, Exp2, Fract2} = '0; // default if not used, to prevent latch
       case (Fmt)
         P.FMT: Packed = Unpacked;
         P.FMT1: begin
@@ -77,8 +76,10 @@ module packoutput import cvw::*;  #(parameter cvw_t P) (
               end
         default: Packed = 'x;
       endcase
+    end
   end else if (P.FPSIZES == 4) begin        
-    always_comb
+    always_comb begin
+      {Exp1, Fract1, Exp2, Fract2, Exp3, Fract3} = '0; // default if not used, to prevent latch
       case (Fmt)
         2'h3: Packed = Unpacked;  // Quad
         2'h1: begin // double
@@ -97,5 +98,6 @@ module packoutput import cvw::*;  #(parameter cvw_t P) (
                 Packed = {{(P.FLEN-P.H_LEN){1'b1}}, Sign, Exp3, Fract3}; 
               end
       endcase
+    end
   end
 endmodule
\ No newline at end of file