From e840edc4e6b9f2a4a4b467ab7eadb56220371650 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 19 Sep 2022 01:02:04 -0700 Subject: [PATCH] Reduced number of cycles needed for division --- pipelined/src/fpu/fdivsqrtfsm.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv index c47158866..d3236e8f1 100644 --- a/pipelined/src/fpu/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrtfsm.sv @@ -95,8 +95,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - if (SqrtE) cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); // ceiling(fbits / r*k) - else cycles = `FPDUR; // *** line above should work once otfc is used to put results in upper bits + cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */