From e81f31776429449a5d873a3dea772debd79c401a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 31 Mar 2022 15:48:15 -0500 Subject: [PATCH] Notes on what to change in ram.sv. --- pipelined/src/uncore/ram.sv | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index e9b0af32d..2d151d50f 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -43,6 +43,13 @@ module ram #(parameter BASE=0, RANGE = 65535) ( output logic HRESPRam, HREADYRam ); + + // Desired changes. + // 1. find a way to merge read and write address into 1 port. + // 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.) + // 3. implement burst. + // 4. remove the configurable latency. + localparam MemStartAddr = BASE>>(1+`XLEN/32); localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);