From e4724b8d0e108c567217099ab2f6ec0547e59b92 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 10 Mar 2024 20:45:27 -0700 Subject: [PATCH] Crypto formatting cleanup --- src/ieu/sha_instructions/sha256sig0.sv | 7 ++----- src/ieu/sha_instructions/sha256sig1.sv | 7 ++----- src/ieu/sha_instructions/sha256sum0.sv | 9 +++------ src/ieu/sha_instructions/sha256sum1.sv | 7 ++----- src/ieu/sha_instructions/sha512sig0.sv | 6 ++---- src/ieu/sha_instructions/sha512sig0h.sv | 10 ++-------- src/ieu/sha_instructions/sha512sig0l.sv | 11 ++--------- src/ieu/sha_instructions/sha512sig1.sv | 4 +--- src/ieu/sha_instructions/sha512sig1h.sv | 11 ++++------- src/ieu/sha_instructions/sha512sig1l.sv | 15 ++++----------- src/ieu/sha_instructions/sha512sum0.sv | 4 +--- src/ieu/sha_instructions/sha512sum0r.sv | 11 ++--------- src/ieu/sha_instructions/sha512sum1.sv | 6 ++---- src/ieu/sha_instructions/sha512sum1r.sv | 13 +++---------- 14 files changed, 32 insertions(+), 89 deletions(-) diff --git a/src/ieu/sha_instructions/sha256sig0.sv b/src/ieu/sha_instructions/sha256sig0.sv index 7b59c4d91..c6760c55b 100644 --- a/src/ieu/sha_instructions/sha256sig0.sv +++ b/src/ieu/sha_instructions/sha256sig0.sv @@ -30,11 +30,8 @@ module sha256sig0 #(parameter WIDTH=32) ( output logic [WIDTH-1:0] result ); - logic [31:0] ror7; - logic [31:0] ror18; - logic [31:0] sh3; - logic [31:0] exts; - + logic [31:0] ror7, ror18, sh3, exts; + assign ror7 = {rs1[6:0], rs1[31:7]}; assign ror18 = {rs1[17:0], rs1[31:18]}; assign sh3 = {3'b0, rs1[31:3]}; diff --git a/src/ieu/sha_instructions/sha256sig1.sv b/src/ieu/sha_instructions/sha256sig1.sv index 8409bc014..ab3f8c0a1 100644 --- a/src/ieu/sha_instructions/sha256sig1.sv +++ b/src/ieu/sha_instructions/sha256sig1.sv @@ -30,14 +30,11 @@ module sha256sig1 #(parameter WIDTH=32) ( output logic [WIDTH-1:0] result ); - logic [31:0] ror17; - logic [31:0] ror19; - logic [31:0] sh10; - logic [31:0] exts; + logic [31:0] ror17, ror19, sh10, exts; assign ror17 = {rs1[16:0], rs1[31:17]}; assign ror19 = {rs1[18:0], rs1[31:19]}; - assign sh10 = {10'b0, rs1[31:10]}; + assign sh10 = {10'b0, rs1[31:10]}; // Assign output to xor of 3 rotates assign exts = ror17 ^ ror19 ^ sh10; diff --git a/src/ieu/sha_instructions/sha256sum0.sv b/src/ieu/sha_instructions/sha256sum0.sv index 8eb4f6018..16240514d 100644 --- a/src/ieu/sha_instructions/sha256sum0.sv +++ b/src/ieu/sha_instructions/sha256sum0.sv @@ -30,12 +30,9 @@ module sha256sum0 #(parameter WIDTH=32) ( output logic [WIDTH-1:0] result ); - logic [31:0] ror2; - logic [31:0] ror13; - logic [31:0] ror22; - logic [31:0] exts; - - assign ror2 = {rs1[1:0], rs1[31:2]}; + logic [31:0] ror2, ror13, ror22, exts; + + assign ror2 = {rs1[1:0], rs1[31:2]}; assign ror13 = {rs1[12:0], rs1[31:13]}; assign ror22 = {rs1[21:0], rs1[31:22]}; diff --git a/src/ieu/sha_instructions/sha256sum1.sv b/src/ieu/sha_instructions/sha256sum1.sv index e7c4c661b..ab9b37b9f 100644 --- a/src/ieu/sha_instructions/sha256sum1.sv +++ b/src/ieu/sha_instructions/sha256sum1.sv @@ -30,11 +30,8 @@ module sha256sum1 #(parameter WIDTH=32) ( output logic [WIDTH-1:0] result ); - logic [31:0] ror6; - logic [31:0] ror11; - logic [31:0] ror25; - logic [31:0] exts; - + logic [31:0] ror6, ror11, ror25, exts; + assign ror6 = {rs1[5:0], rs1[31:6]}; assign ror11 = {rs1[10:0], rs1[31:11]}; assign ror25 = {rs1[24:0], rs1[31:25]}; diff --git a/src/ieu/sha_instructions/sha512sig0.sv b/src/ieu/sha_instructions/sha512sig0.sv index 91e7ba6c8..762ca7b3c 100644 --- a/src/ieu/sha_instructions/sha512sig0.sv +++ b/src/ieu/sha_instructions/sha512sig0.sv @@ -30,11 +30,9 @@ module sha512sig0( output logic [63:0] result ); - logic [63:0] ror1; - logic [63:0] ror8; - logic [63:0] sh7; + logic [63:0] ror1, ror8, sh7; - assign ror1 = {rs1[0], rs1[63:1]}; + assign ror1 = {rs1[0], rs1[63:1]}; assign ror8 = {rs1[7:0], rs1[63:8]}; assign sh7 = rs1 >> 7; diff --git a/src/ieu/sha_instructions/sha512sig0h.sv b/src/ieu/sha_instructions/sha512sig0h.sv index 183b8e3f3..5b3b8555e 100644 --- a/src/ieu/sha_instructions/sha512sig0h.sv +++ b/src/ieu/sha_instructions/sha512sig0h.sv @@ -31,14 +31,8 @@ module sha512sig0h( output logic [31:0] DataOut ); - // RS1 Shifts - logic [31:0] shift1; - logic [31:0] shift7; - logic [31:0] shift8; - - // RS2 Shifts - logic [31:0] shift31; - logic [31:0] shift24; + logic [31:0] shift1, shift7, shift8; // rs1 shifts + logic [31:0] shift31, shift24; // rs2 shifts // Shift rs1 assign shift1 = rs1 >> 1; diff --git a/src/ieu/sha_instructions/sha512sig0l.sv b/src/ieu/sha_instructions/sha512sig0l.sv index 4ec09bcc0..6a5796e66 100644 --- a/src/ieu/sha_instructions/sha512sig0l.sv +++ b/src/ieu/sha_instructions/sha512sig0l.sv @@ -31,15 +31,8 @@ module sha512sig0l( output logic [31:0] DataOut ); - // rs1 operations - logic [31:0] shift1; - logic [31:0] shift7; - logic [31:0] shift8; - - // rs2 operations - logic [31:0] shift31; - logic [31:0] shift25; - logic [31:0] shift24; + logic [31:0] shift1, shift7, shift8; // rs1 shifts + logic [31:0] shift31, shift25, shift24; // rs2 shifts // rs1 shifts assign shift1 = rs1 >> 1; diff --git a/src/ieu/sha_instructions/sha512sig1.sv b/src/ieu/sha_instructions/sha512sig1.sv index cd99a2944..63836079a 100644 --- a/src/ieu/sha_instructions/sha512sig1.sv +++ b/src/ieu/sha_instructions/sha512sig1.sv @@ -30,9 +30,7 @@ module sha512sig1( output logic [63:0] result ); - logic [63:0] ror19; - logic [63:0] ror61; - logic [63:0] sh6; + logic [63:0] ror19, ror61, sh6; assign ror19 = {rs1[18:0], rs1[63:19]}; assign ror61 = {rs1[60:0], rs1[63:61]}; diff --git a/src/ieu/sha_instructions/sha512sig1h.sv b/src/ieu/sha_instructions/sha512sig1h.sv index 9e6b966ca..e424018a7 100644 --- a/src/ieu/sha_instructions/sha512sig1h.sv +++ b/src/ieu/sha_instructions/sha512sig1h.sv @@ -31,18 +31,15 @@ module sha512sig1h( output logic [31:0] DataOut ); - // rs1 shifts - logic [31:0] shift3; - logic [31:0] shift6; - logic [31:0] shift19; - // rs2 shifts - logic [31:0] shift29; - logic [31:0] shift13; + + logic [31:0] shift3, shift6, shift19; // rs1 shifts + logic [31:0] shift29, shift13; // rs2 shifts // shift rs1 assign shift3 = rs1 << 3; assign shift6 = rs1 >> 6; assign shift19 = rs1 >> 19; + // shift rs2 assign shift29 = rs2 >> 29; assign shift13 = rs2 << 13; diff --git a/src/ieu/sha_instructions/sha512sig1l.sv b/src/ieu/sha_instructions/sha512sig1l.sv index c836e45f5..05c5799e3 100644 --- a/src/ieu/sha_instructions/sha512sig1l.sv +++ b/src/ieu/sha_instructions/sha512sig1l.sv @@ -31,19 +31,12 @@ module sha512sig1l( output logic [31:0] DataOut ); - // rs1 shift logic - logic [31:0] shift3; - logic [31:0] shift6; - logic [31:0] shift19; - - // rs2 shift logics - logic [31:0] shift29; - logic [31:0] shift26; - logic [31:0] shift13; + logic [31:0] shift3, shift6, shift19; // rs1 shifts + logic [31:0] shift29, shift26, shift13; // Shift rs1 - assign shift3 = rs1 << 3; - assign shift6 = rs1 >> 6; + assign shift3 = rs1 << 3; + assign shift6 = rs1 >> 6; assign shift19 = rs1 >> 19; // Shift rs2 diff --git a/src/ieu/sha_instructions/sha512sum0.sv b/src/ieu/sha_instructions/sha512sum0.sv index a974cbb2b..e364d9c9b 100644 --- a/src/ieu/sha_instructions/sha512sum0.sv +++ b/src/ieu/sha_instructions/sha512sum0.sv @@ -30,9 +30,7 @@ module sha512sum0( output logic [63:0] result ); - logic [63:0] ror28; - logic [63:0] ror34; - logic [63:0] ror39; + logic [63:0] ror28, ror34, ror39; assign ror28 = {rs1[27:0], rs1[63:28]}; assign ror34 = {rs1[33:0], rs1[63:34]}; diff --git a/src/ieu/sha_instructions/sha512sum0r.sv b/src/ieu/sha_instructions/sha512sum0r.sv index ab359d7e0..a64b7678a 100644 --- a/src/ieu/sha_instructions/sha512sum0r.sv +++ b/src/ieu/sha_instructions/sha512sum0r.sv @@ -31,15 +31,8 @@ module sha512sum0r( output logic [31:0] DataOut ); - // RS1 shifts - logic [31:0] shift25; - logic [31:0] shift30; - logic [31:0] shift28; - - // RS2 shifts - logic [31:0] shift7; - logic [31:0] shift2; - logic [31:0] shift4; + logic [31:0] shift25, shift30, shift28; // rs1 shifts + logic [31:0] shift7, shift2, shift4; // rs2 shifts // Shift rs1 assign shift25 = rs1 << 25; diff --git a/src/ieu/sha_instructions/sha512sum1.sv b/src/ieu/sha_instructions/sha512sum1.sv index 21d0630e1..5c33f828c 100644 --- a/src/ieu/sha_instructions/sha512sum1.sv +++ b/src/ieu/sha_instructions/sha512sum1.sv @@ -30,10 +30,8 @@ module sha512sum1( output logic [63:0] result ); - logic [63:0] ror14; - logic [63:0] ror18; - logic [63:0] ror41; - + logic [63:0] ror14, ror18, ror41; + assign ror14 = {rs1[13:0], rs1[63:14]}; assign ror18 = {rs1[17:0], rs1[63:18]}; assign ror41 = {rs1[40:0], rs1[63:41]}; diff --git a/src/ieu/sha_instructions/sha512sum1r.sv b/src/ieu/sha_instructions/sha512sum1r.sv index 187dd1ef5..ce06bb163 100644 --- a/src/ieu/sha_instructions/sha512sum1r.sv +++ b/src/ieu/sha_instructions/sha512sum1r.sv @@ -31,15 +31,8 @@ module sha512sum1r( output logic [31:0] DataOut ); - // Declare logic for rs1 shifts - logic [31:0] shift1by23; - logic [31:0] shift1by14; - logic [31:0] shift1by18; - - // Declare logic for rs2 shifts - logic [31:0] shift2by9; - logic [31:0] shift2by18; - logic [31:0] shift2by14; + logic [31:0] shift1by23, shift1by14, shift1by18; // rs1 shifts + logic [31:0] shift2by9, shift2by18, shift2by14; // rs2 shifts // Shift RS1 assign shift1by23 = rs1 << 23; @@ -47,7 +40,7 @@ module sha512sum1r( assign shift1by18 = rs1 >> 18; // Shift RS2 - assign shift2by9 = rs2 >> 9; + assign shift2by9 = rs2 >> 9; assign shift2by18 = rs2 << 18; assign shift2by14 = rs2 << 14;