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Added named support for Zicntr and Zihpm

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This commit is contained in:
David Harris 2023-06-09 09:35:51 -07:00
parent 1c547fc02e
commit e2e6f6f255
12 changed files with 27 additions and 18 deletions
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3
config/buildroot/config.vh
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@ -40,7 +40,8 @@ localparam IEEE754 = 0;
localparam MISA = (32'h0014112D); localparam MISA = (32'h0014112D);
localparam ZICSR_SUPPORTED = 1; localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1;
localparam ZICOUNTERS_SUPPORTED = 1; localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam COUNTERS = 12'd32; localparam COUNTERS = 12'd32;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

3
config/rv32e/config.vh
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@ -41,7 +41,8 @@ localparam MISA = (32'h00000010);
localparam ZICSR_SUPPORTED = 0; localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd0; localparam COUNTERS = 12'd0;
localparam ZICOUNTERS_SUPPORTED = 0; localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

3
config/rv32gc/config.vh
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@ -42,7 +42,8 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 |
localparam ZICSR_SUPPORTED = 1; localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32; localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1; localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1; localparam SSTC_SUPPORTED = 1;

5
config/rv32i/config.vh
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@ -40,8 +40,9 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104); localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0; localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32; localparam COUNTERS = 0;
localparam ZICOUNTERS_SUPPORTED = 0; localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

3
config/rv32imc/config.vh
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@ -40,7 +40,8 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
localparam ZICSR_SUPPORTED = 1; localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32; localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1; localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

3
config/rv64fpquad/config.vh
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@ -41,7 +41,8 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20
localparam ZICSR_SUPPORTED = 1; localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32; localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1; localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 1; localparam ZFH_SUPPORTED = 1;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

3
config/rv64gc/config.vh
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@ -44,7 +44,8 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12
localparam ZICSR_SUPPORTED = 1; localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32; localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1; localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1; localparam SSTC_SUPPORTED = 1;

5
config/rv64i/config.vh
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@ -40,8 +40,9 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104); localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0; localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32; localparam COUNTERS = 0;
localparam ZICOUNTERS_SUPPORTED = 0; localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0;

2
src/ifu/bpred/bpred.sv
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@ -191,7 +191,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
else assign NextValidPCE = PCE; else assign NextValidPCE = PCE;
if(P.ZICOUNTERS_SUPPORTED) begin if(P.ZIHPM_SUPPORTED) begin
logic [P.XLEN-1:0] RASPCD, RASPCE; logic [P.XLEN-1:0] RASPCD, RASPCE;
logic BTAWrongE, RASPredPCWrongE; logic BTAWrongE, RASPredPCWrongE;
// performance counters // performance counters

2
src/privileged/csr.sv
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@ -266,7 +266,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign IllegalCSRUAccessM = 1; assign IllegalCSRUAccessM = 1;
end end
if (P.ZICOUNTERS_SUPPORTED) begin:counters if (P.ZICNTR_SUPPORTED) begin:counters
csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM, csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,

8
src/privileged/csrc.sv
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@ -92,9 +92,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[0] = 1'b1; // MCYCLE always increments assign CounterEvent[0] = 1'b1; // MCYCLE always increments
assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired
if(P.QEMU) begin: cevent // No other performance counters in QEMU if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters
assign CounterEvent[P.COUNTERS-1:3] = 0;
end else begin: cevent // User-defined counters
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
@ -121,6 +119,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle
// coverage on // coverage on
assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end else begin: cevent
assign CounterEvent[P.COUNTERS-1:3] = 0;
end end
// Counter update and write logic // Counter update and write logic
@ -165,7 +165,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
IllegalCSRCAccessM = 1; // requested CSR doesn't exist IllegalCSRCAccessM = 1; // requested CSR doesn't exist
end end
end else begin // 32-bit counter reads end else begin // 32-bit counter reads
// Veri lator doesn't realize this only occurs for XLEN=32 // Veril ator doesn't realize this only occurs for XLEN=32
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32]; else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];

5
src/wally/cvw.sv
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@ -47,8 +47,9 @@ typedef struct packed {
// RISC-V Features // RISC-V Features
logic ZICSR_SUPPORTED; logic ZICSR_SUPPORTED;
logic ZIFENCEI_SUPPORTED; logic ZIFENCEI_SUPPORTED;
logic [11:0] COUNTERS; logic [11:0] COUNTERS;
logic ZICOUNTERS_SUPPORTED; logic ZICNTR_SUPPORTED;
logic ZIHPM_SUPPORTED;
logic ZFH_SUPPORTED; logic ZFH_SUPPORTED;
logic SSTC_SUPPORTED; logic SSTC_SUPPORTED;
logic VIRTMEM_SUPPORTED; logic VIRTMEM_SUPPORTED;