From e2e6f6f25513565c645a0db303ff63093b68c78e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 9 Jun 2023 09:35:51 -0700 Subject: [PATCH] Added named support for Zicntr and Zihpm --- config/buildroot/config.vh | 3 ++- config/rv32e/config.vh | 3 ++- config/rv32gc/config.vh | 3 ++- config/rv32i/config.vh | 5 +++-- config/rv32imc/config.vh | 3 ++- config/rv64fpquad/config.vh | 3 ++- config/rv64gc/config.vh | 3 ++- config/rv64i/config.vh | 5 +++-- src/ifu/bpred/bpred.sv | 2 +- src/privileged/csr.sv | 2 +- src/privileged/csrc.sv | 8 ++++---- src/wally/cvw.sv | 5 +++-- 12 files changed, 27 insertions(+), 18 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index f5a1b6421..8aa6d0435 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -40,7 +40,8 @@ localparam IEEE754 = 0; localparam MISA = (32'h0014112D); localparam ZICSR_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1; -localparam ZICOUNTERS_SUPPORTED = 1; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; localparam COUNTERS = 12'd32; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index b2e45562e..680e4355f 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -41,7 +41,8 @@ localparam MISA = (32'h00000010); localparam ZICSR_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0; localparam COUNTERS = 12'd0; -localparam ZICOUNTERS_SUPPORTED = 0; +localparam ZICNTR_SUPPORTED = 0; +localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 23c865c8c..00619c936 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -42,7 +42,8 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | localparam ZICSR_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 1; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index bd307f17d..0ca375051 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -40,8 +40,9 @@ localparam IEEE754 = 0; localparam MISA = (32'h00000104); localparam ZICSR_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0; -localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 0; +localparam COUNTERS = 0; +localparam ZICNTR_SUPPORTED = 0; +localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index d49fa7ec3..317c642a9 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -40,7 +40,8 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12); localparam ZICSR_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 1; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 655fab9b6..e29f3fb3b 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -41,7 +41,8 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 localparam ZICSR_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 1; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 1; localparam SSTC_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 923cd08d3..34c824270 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -44,7 +44,8 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 localparam ZICSR_SUPPORTED = 1; localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 1; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index d2914c966..204fb172a 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -40,8 +40,9 @@ localparam IEEE754 = 0; localparam MISA = (32'h00000104); localparam ZICSR_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0; -localparam COUNTERS = 12'd32; -localparam ZICOUNTERS_SUPPORTED = 0; +localparam COUNTERS = 0; +localparam ZICNTR_SUPPORTED = 0; +localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 2bc65caa6..7493c5ccc 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -191,7 +191,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); else assign NextValidPCE = PCE; - if(P.ZICOUNTERS_SUPPORTED) begin + if(P.ZIHPM_SUPPORTED) begin logic [P.XLEN-1:0] RASPCD, RASPCE; logic BTAWrongE, RASPredPCWrongE; // performance counters diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 4eacc4d0a..3cc150fc0 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -266,7 +266,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign IllegalCSRUAccessM = 1; end - if (P.ZICOUNTERS_SUPPORTED) begin:counters + if (P.ZICNTR_SUPPORTED) begin:counters csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index e1104f699..f6f228dd8 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -92,9 +92,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[0] = 1'b1; // MCYCLE always increments assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired - if(P.QEMU) begin: cevent // No other performance counters in QEMU - assign CounterEvent[P.COUNTERS-1:3] = 0; - end else begin: cevent // User-defined counters + if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions @@ -121,6 +119,8 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle // coverage on assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions + end else begin: cevent + assign CounterEvent[P.COUNTERS-1:3] = 0; end // Counter update and write logic @@ -165,7 +165,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( IllegalCSRCAccessM = 1; // requested CSR doesn't exist end end else begin // 32-bit counter reads - // Veri lator doesn't realize this only occurs for XLEN=32 + // Veril ator doesn't realize this only occurs for XLEN=32 /* verilator lint_off WIDTH */ if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32]; diff --git a/src/wally/cvw.sv b/src/wally/cvw.sv index f58f7814f..e61c8b9ce 100644 --- a/src/wally/cvw.sv +++ b/src/wally/cvw.sv @@ -47,8 +47,9 @@ typedef struct packed { // RISC-V Features logic ZICSR_SUPPORTED; logic ZIFENCEI_SUPPORTED; - logic [11:0] COUNTERS; - logic ZICOUNTERS_SUPPORTED; + logic [11:0] COUNTERS; + logic ZICNTR_SUPPORTED; + logic ZIHPM_SUPPORTED; logic ZFH_SUPPORTED; logic SSTC_SUPPORTED; logic VIRTMEM_SUPPORTED;