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Corrects merge error in Arty A7 clock speed.

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This commit is contained in:
Rose Thompson 2024-09-02 15:01:41 -07:00
parent 8375e168c0
commit e29e1feed5
1 changed files with 2 additions and 1 deletions
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3
fpga/generator/mmcm.tcl
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@ -1,5 +1,6 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
set ipName mmcm
@ -15,7 +16,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {$SYSTEMCLOCK} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName]