From e29e1feed51cc8419107129f7aa1a43511ad5526 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 2 Sep 2024 15:01:41 -0700 Subject: [PATCH] Corrects merge error in Arty A7 clock speed. --- fpga/generator/mmcm.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fpga/generator/mmcm.tcl b/fpga/generator/mmcm.tcl index de4a1a1d0..f5a7da06f 100644 --- a/fpga/generator/mmcm.tcl +++ b/fpga/generator/mmcm.tcl @@ -1,5 +1,6 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) +set SYSTEMCLOCK $::env(SYSTEMCLOCK) set ipName mmcm @@ -15,7 +16,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {$SYSTEMCLOCK} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName]