Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Corrects merge error in Arty A7 clock speed.

Browse Source
This commit is contained in:
Rose Thompson 2024-09-02 15:01:41 -07:00
parent 8375e168c0
commit e29e1feed5
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
fpga/generator/mmcm.tcl
View File

@ -1,5 +1,6 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
set ipName mmcm set ipName mmcm
@ -15,7 +16,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {$SYSTEMCLOCK} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKIN1_JITTER_PS {10.0} \ CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName] ] [get_ips $ipName]