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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2021-05-03 19:37:56 -04:00
commit e265aa4d41
3 changed files with 21 additions and 14 deletions
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12
wally-pipelined/config/coremark_bare/wally-config.vh
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@ -57,7 +57,8 @@
`define MEM_DCACHE 0 `define MEM_DCACHE 0
`define MEM_DTIM 1 `define MEM_DTIM 1
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000
@ -85,7 +86,7 @@
// Test modes // Test modes
// Tie GPIO outputs back to inputs // Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0 `define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim // Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0 `define OVPSIM_CSR_CONFIG 0
@ -94,7 +95,10 @@
`define UART_PRESCALE 1 `define UART_PRESCALE 1
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 53 `define PLIC_NUM_SRC 4
//comment out the following if >= 32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4 `define PLIC_UART_ID 4
/* verilator lint_off STMTDLY */ /* verilator lint_off STMTDLY */
@ -105,5 +109,5 @@
`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
`define BPRED_ENABLED 1 `define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" `define BPTYPE "BPGSHARE"//comments
`define TESTSBP 0 `define TESTSBP 0

6
wally-pipelined/regression/wally-coremark_bare.do
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@ -35,6 +35,8 @@ vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../
vopt +acc work.testbench -o workopt vopt +acc work.testbench -o workopt
vsim workopt vsim workopt
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
view wave view wave
-- display input and output signals as hexidecimal values -- display input and output signals as hexidecimal values
@ -54,7 +56,7 @@ add wave -divider
add wave -divider Fetch add wave -divider Fetch
add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/PCF
add wave -hex /testbench/dut/hart/ifu/InstrF add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
add wave /testbench/InstrFName add wave /testbench/InstrFName
add wave -divider Decode add wave -divider Decode
add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/PCD
@ -90,7 +92,7 @@ add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
add wave -divider Regfile_itself add wave -divider Regfile_itself
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
add wave -divider RAM add wave -divider RAM
add wave -hex -r /testbench/dut/uncore/dtim/RAM #add wave -hex -r /testbench/dut/uncore/dtim/RAM
add wave -divider Misc add wave -divider Misc
add wave -divider add wave -divider
#add wave -hex -r /testbench/* #add wave -hex -r /testbench/*

17
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -48,7 +48,7 @@ module testbench();
// pick tests based on modes supported // pick tests based on modes supported
initial initial
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"}; tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
string signame, memfilename; string signame, memfilename;
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout; logic UARTSin, UARTSout;
@ -65,7 +65,7 @@ module testbench();
// Track names of instructions // Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.InstrF, dut.hart.ifu.icache.controller.FinalInstrRawF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, InstrW, dut.hart.ifu.InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
@ -81,11 +81,12 @@ module testbench();
// read test vectors into memory // read test vectors into memory
memfilename = tests[0]; memfilename = tests[0];
$readmemh(memfilename, dut.uncore.dtim.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=268437702; j < 268566528; j = j+1) //for(j=268437955; j < 268566528; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0; //dut.uncore.dtim.RAM[j] = 64'b0;
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
reset = 1; # 22; reset = 0; //dut.uncore.dtim.RAM[268437713]=64'b1;
reset = 1; # 22; reset = 0;
end end
// generate clock to sequence tests // generate clock to sequence tests
always always
@ -94,7 +95,7 @@ module testbench();
end end
always @(negedge clk) always @(negedge clk)
begin begin
if (dut.hart.priv.ebreakM) begin if (dut.hart.priv.ecallM) begin
#20; #20;
$display("Code ended with ebreakM"); $display("Code ended with ebreakM");
$stop; $stop;
@ -102,8 +103,8 @@ module testbench();
end end
initial begin initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
end end
endmodule endmodule