From 463ba1a2be3dbd2fd1800007d501649a199c7021 Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Wed, 14 Apr 2021 23:09:37 -0400 Subject: [PATCH 1/5] coremark directory changes --- wally-pipelined/regression/wally-coremark_bare.do | 4 ++-- wally-pipelined/testbench/testbench-coremark_bare.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 9318c494a..64e20c1f2 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -54,7 +54,7 @@ add wave -divider add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/dut/hart/ifu/InstrF +add wave -hex /testbench/dut/hart/ifu/ic/InstrF add wave /testbench/InstrFName add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -#add wave -hex -r /testbench/* +add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 3f2af76b6..860820bfd 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -48,7 +48,7 @@ module testbench(); // pick tests based on modes supported initial - tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"}; + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"}; string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -65,7 +65,7 @@ module testbench(); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.InstrF, + dut.hart.ifu.ic.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); From 2a33673e3ce6f0298a849da0519967d33f99c72d Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Wed, 28 Apr 2021 14:21:53 -0400 Subject: [PATCH 4/5] coremark updates --- wally-pipelined/testbench/testbench-coremark_bare.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 860820bfd..e7dbb9008 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -81,11 +81,12 @@ module testbench(); // read test vectors into memory memfilename = tests[0]; $readmemh(memfilename, dut.uncore.dtim.RAM); - for(j=268437702; j < 268566528; j = j+1) - dut.uncore.dtim.RAM[j] = 64'b0; + //for(j=268437955; j < 268566528; j = j+1) + //dut.uncore.dtim.RAM[j] = 64'b0; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab"; - reset = 1; # 22; reset = 0; + //dut.uncore.dtim.RAM[268437713]=64'b1; + reset = 1; # 22; reset = 0; end // generate clock to sequence tests always @@ -94,7 +95,7 @@ module testbench(); end always @(negedge clk) begin - if (dut.hart.priv.ebreakM) begin + if (dut.hart.priv.ecallM) begin #20; $display("Code ended with ebreakM"); $stop; From 2d1d9294851bd7eddb2c24ad5c7f5bc65b110a26 Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Mon, 3 May 2021 19:27:34 -0400 Subject: [PATCH 5/5] coremark print statment --- wally-pipelined/config/coremark_bare/wally-config.vh | 12 ++++++++---- wally-pipelined/regression/wally-coremark_bare.do | 8 +++++--- wally-pipelined/testbench/testbench-coremark_bare.sv | 6 +++--- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index a6d64c6be..b42dd678d 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -57,7 +57,8 @@ `define MEM_DCACHE 0 `define MEM_DTIM 1 `define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 +`define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -85,7 +86,7 @@ // Test modes // Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 +`define GPIO_LOOPBACK_TEST 1 // Busybear special CSR config to match OVPSim `define OVPSIM_CSR_CONFIG 0 @@ -94,7 +95,10 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 53 +`define PLIC_NUM_SRC 4 +//comment out the following if >= 32 sources +`define PLIC_NUM_SRC_LT_32 +`define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 /* verilator lint_off STMTDLY */ @@ -105,5 +109,5 @@ `define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" +`define BPTYPE "BPGSHARE"//comments `define TESTSBP 0 diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 64e20c1f2..3f71fcbdf 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -35,6 +35,8 @@ vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../ vopt +acc work.testbench -o workopt vsim workopt +mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM + view wave -- display input and output signals as hexidecimal values @@ -54,7 +56,7 @@ add wave -divider add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/dut/hart/ifu/ic/InstrF +add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave /testbench/InstrFName add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD @@ -90,10 +92,10 @@ add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* add wave -divider Regfile_itself add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf add wave -divider RAM -add wave -hex -r /testbench/dut/uncore/dtim/RAM +#add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -add wave -hex -r /testbench/* +#add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index e7dbb9008..c0441eb24 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -65,7 +65,7 @@ module testbench(); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.ic.InstrF, + dut.hart.ifu.icache.controller.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); @@ -103,8 +103,8 @@ module testbench(); end initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); - $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); + $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); + $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); end endmodule