RAS is now compliant with our header and documentation guide.

This commit is contained in:
Ross Thompson 2023-01-25 17:18:07 -06:00
parent 0b9f787635
commit e1d0be5c61

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@ -1,13 +1,14 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// RASPredictor.sv // RASPredictor.sv
// //
// Written: Ross Thomposn // Written: Ross Thomposn ross1728@gmail.com
// Email: ross1728@gmail.com // Created: 15 February 2021
// Created: February 15, 2021 // Modified: 25 January 2023
// Modified:
// //
// Purpose: 2 bit saturating counter predictor with parameterized table depth. // Purpose: 2 bit saturating counter predictor with parameterized table depth.
// //
// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -28,41 +29,42 @@
`include "wally-config.vh" `include "wally-config.vh"
module RASPredictor module RASPredictor #(parameter int StackSize = 16
#(parameter int StackSize = 16 )(input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong
output logic [`XLEN-1:0] RASPCF, input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class
input logic [3:0] WrongPredInstrClassD, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, output logic [`XLEN-1:0] RASPCF // Top of the stack
input logic [`XLEN-1:0] PCLinkE
); );
// *** need to repair popped and then flushed returns.
logic CounterEn; logic CounterEn;
localparam Depth = $clog2(StackSize); localparam Depth = $clog2(StackSize);
logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1;
logic [StackSize-1:0] [`XLEN-1:0] memory; logic [StackSize-1:0] [`XLEN-1:0] memory;
integer index; integer index;
logic PopF; logic PopF;
logic PushE; logic PushE;
logic RepairD; logic RepairD;
logic PossibleRepairD;
logic DecrementPtr;
assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
assign RepairD = InstrClassD[2] & ~StallE & ~FlushE; assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE;
assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE;
assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; assign CounterEn = PopF | PushE | RepairD;
assign PtrD = PopF | RepairD ? PtrM1 : PtrP1; assign DecrementPtr = PopF | PossibleRepairD;
mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
assign PtrM1 = PtrQ - 1'b1; assign PtrM1 = PtrQ - 1'b1;
assign PtrP1 = PtrQ + 1'b1; assign PtrP1 = PtrQ + 1'b1;
// *** what happens if jal is executing and there is a return being flushed in Decode?
flopenr #(Depth) PTR(.clk(clk), flopenr #(Depth) PTR(.clk(clk),
.reset(reset), .reset(reset),