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Added logic for the non-cache atomics.

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Rose Thompson 2024-01-15 17:47:17 -06:00
parent 82a786f185
commit dfe5ef4427
4 changed files with 20 additions and 13 deletions
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3
src/ebu/ahbinterface.sv
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@ -44,6 +44,7 @@ module ahbinterface #(
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
input logic BusAtomic, // Uncache atomic memory operation
input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word
input logic [XLEN-1:0] WriteData, // IEU write data for a store input logic [XLEN-1:0] WriteData, // IEU write data for a store
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
@ -64,7 +65,7 @@ module ahbinterface #(
assign HWSTRB = '0; assign HWSTRB = '0;
end end
busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic,
.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE); .HTRANS, .HWRITE);

26
src/ebu/busfsm.sv
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@ -38,6 +38,7 @@ module busfsm #(
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
input logic BusAtomic, // Uncache atomic memory operation
output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
@ -47,7 +48,7 @@ module busfsm #(
output logic HWRITE // AHB 0: Read operation 1: Write operation output logic HWRITE // AHB 0: Read operation 1: Write operation
); );
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype; typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, ATOMIC_PHASE} busstatetype;
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
busstatetype CurrState, NextState; busstatetype CurrState, NextState;
@ -58,13 +59,16 @@ module busfsm #(
always_comb begin always_comb begin
case(CurrState) case(CurrState)
ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3; DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_PHASE;
else NextState = DATA_PHASE; else if(HREADY & ~BusAtomic) NextState = MEM3;
MEM3: if(Stall) NextState = MEM3; else NextState = DATA_PHASE;
else NextState = ADR_PHASE; ATOMIC_PHASE: if(HREADY) NextState = MEM3;
default: NextState = ADR_PHASE; else NextState = ATOMIC_PHASE;
MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE;
default: NextState = ADR_PHASE;
endcase endcase
end end
@ -74,8 +78,10 @@ module busfsm #(
assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3); assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3);
assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE; assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) |
assign HWRITE = BusRW[0]; (CurrState == DATA_PHASE & BusAtomic) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = (BusRW[0] & ~BusAtomic) | (CurrState == DATA_PHASE & BusAtomic);
assign CaptureEn = CurrState == DATA_PHASE; assign CaptureEn = CurrState == DATA_PHASE;
endmodule endmodule

2
src/ifu/ifu.sv
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@ -275,7 +275,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
assign CacheCommittedF = '0; assign CacheCommittedF = '0;

2
src/lsu/lsu.sv
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@ -369,7 +369,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
// Mux between the 2 sources of read data, 0: Bus, 1: DTIM // Mux between the 2 sources of read data, 0: Bus, 1: DTIM