From dfe5ef44276af447c32c510aae47e02350d16093 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 15 Jan 2024 17:47:17 -0600 Subject: [PATCH] Added logic for the non-cache atomics. --- src/ebu/ahbinterface.sv | 3 ++- src/ebu/busfsm.sv | 26 ++++++++++++++++---------- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- 4 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index fa5a6293e..df84175f0 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -44,6 +44,7 @@ module ahbinterface #( input logic Stall, // Core pipeline is stalled input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic BusAtomic, // Uncache atomic memory operation input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word input logic [XLEN-1:0] WriteData, // IEU write data for a store output logic BusStall, // Bus is busy with an in flight memory operation @@ -64,7 +65,7 @@ module ahbinterface #( assign HWSTRB = '0; end - busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, + busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 9ba159705..126759b0d 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -38,6 +38,7 @@ module busfsm #( input logic Stall, // Core pipeline is stalled input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic BusAtomic, // Uncache atomic memory operation output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA output logic BusStall, // Bus is busy with an in flight memory operation output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt @@ -47,7 +48,7 @@ module busfsm #( output logic HWRITE // AHB 0: Read operation 1: Write operation ); - typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype; + typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, ATOMIC_PHASE} busstatetype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; busstatetype CurrState, NextState; @@ -58,13 +59,16 @@ module busfsm #( always_comb begin case(CurrState) - ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; - else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY) NextState = MEM3; - else NextState = DATA_PHASE; - MEM3: if(Stall) NextState = MEM3; - else NextState = ADR_PHASE; - default: NextState = ADR_PHASE; + ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; + else NextState = ADR_PHASE; + DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_PHASE; + else if(HREADY & ~BusAtomic) NextState = MEM3; + else NextState = DATA_PHASE; + ATOMIC_PHASE: if(HREADY) NextState = MEM3; + else NextState = ATOMIC_PHASE; + MEM3: if(Stall) NextState = MEM3; + else NextState = ADR_PHASE; + default: NextState = ADR_PHASE; endcase end @@ -74,8 +78,10 @@ module busfsm #( assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3); - assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE; - assign HWRITE = BusRW[0]; + assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) | + (CurrState == DATA_PHASE & BusAtomic) ? AHB_NONSEQ : AHB_IDLE; + assign HWRITE = (BusRW[0] & ~BusAtomic) | (CurrState == DATA_PHASE & BusAtomic); + assign CaptureEn = CurrState == DATA_PHASE; endmodule diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 8e7d9a0d1..0bd899306 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -275,7 +275,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), - .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), + .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0), .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); assign CacheCommittedF = '0; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index cf0fab9e8..f86c62aea 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -369,7 +369,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), - .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]), + .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); // Mux between the 2 sources of read data, 0: Bus, 1: DTIM