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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #599 from davidharrishmc/dev
More coverage: CacheWay, hptw
This commit is contained in:
commit
df8df0598d
@ -93,6 +93,11 @@ for {set i 0} {$i < $numcacheways} {incr i} {
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# below: flushD can't go high during an icache write b/c of pipeline stall
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# below: flushD can't go high during an icache write b/c of pipeline stall
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
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# No CMO to clear valid bits of I$
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"]
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
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# No dirty ways in read-only I$
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
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}
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}
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## D$ Exclusions.
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## D$ Exclusions.
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@ -104,6 +109,8 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get
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set numcacheways 4
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set numcacheways 4
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for {set i 0} {$i < $numcacheways} {incr i} {
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for {set i 0} {$i < $numcacheways} {incr i} {
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
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# InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
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# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
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# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
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# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
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# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
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@ -246,6 +253,9 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang
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# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
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# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
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coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
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coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
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###############
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###############
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# HPTW exclusions
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# HPTW exclusions
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###############
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###############
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5
src/cache/cache.sv
vendored
5
src/cache/cache.sv
vendored
@ -199,7 +199,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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// Flush logic
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// Flush logic
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (!READ_ONLY_CACHE) begin:flushlogic
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if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed
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// Flush address (line number)
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// Flush address (line number)
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assign ResetOrFlushCntRst = reset | FlushCntRst;
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assign ResetOrFlushCntRst = reset | FlushCntRst;
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flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
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flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
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@ -213,7 +213,8 @@ module cache import cvw::*; #(parameter cvw_t P,
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else assign NextFlushWay = FlushWay[NUMWAYS-1];
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else assign NextFlushWay = FlushWay[NUMWAYS-1];
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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end // block: flushlogic
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end // block: flushlogic
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else begin:flushlogic
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else begin:flushlogic // I$ is never flushed because it is never dirty
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assign FlushWay = 0;
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assign FlushWayFlag = 0;
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assign FlushWayFlag = 0;
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assign FlushAdrFlag = 0;
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assign FlushAdrFlag = 0;
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end
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end
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8
src/cache/cacheway.sv
vendored
8
src/cache/cacheway.sv
vendored
@ -100,7 +100,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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assign SetValidWay = SetValid & SelData;
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assign SetValidWay = SetValid & SelData;
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assign ClearValidWay = ClearValid & SelData;
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assign ClearValidWay = ClearValid & SelData; // exclusion-tag: icache ClearValidWay
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assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
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assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
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assign ClearDirtyWay = ClearDirty & SelData;
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assign ClearDirtyWay = ClearDirty & SelData;
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
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@ -121,8 +121,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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// AND portion of distributed tag multiplexer
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// AND portion of distributed tag multiplexer
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assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
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assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
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assign HitDirtyWay = Dirty & ValidWay;
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assign HitDirtyWay = Dirty & ValidWay;
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assign DirtyWay = SelDirty & HitDirtyWay;
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assign DirtyWay = SelDirty & HitDirtyWay; // exclusion-tag: icache DirtyWay
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay;
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; // exclusion-tag: dcache HitWay
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flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
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flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
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@ -163,7 +163,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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ValidWay <= #1 ValidBits[CacheSetTag];
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ValidWay <= #1 ValidBits[CacheSetTag];
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if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
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if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
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else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay;
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else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay;
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else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0;
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else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; // exclusion-tag: icache ClearValidBits
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end
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end
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end
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end
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18
tests/coverage/fround.S
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18
tests/coverage/fround.S
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@ -0,0 +1,18 @@
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// fround.s
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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bseti t0, zero, 14 # turn on FPU
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csrs mstatus, t0
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# test fround behavior on NaN
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li t0, 0x7FC00001
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fmv.w.x ft0, t0
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fround.s ft1, ft0
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j done
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.align 10
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data_start:
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@ -74,8 +74,31 @@ main:
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.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
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.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
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# exercise all the cache ways
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j way0code
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# stress test cache ways by loading stuff from each one and then doing fence.i to invalidate
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.align 12
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way0code:
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jal way1code
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fence.i
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j done
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.align 12
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way1code:
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j way2code
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.align 12
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way2code:
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j way3code
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.align 12
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way3code:
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j way00code
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.align 12
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way00code:
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ret
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j done
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j done
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@ -133,10 +133,18 @@ main:
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li t0, 0x1000000000
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li t0, 0x1000000000
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lw t1, 0(t0)
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lw t1, 0(t0)
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# Bad PBMT on top level PTE
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li t0, 0x1800000000
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lw t1, 0(t0)
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# Access fault on megapage
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# Access fault on megapage
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li t0, 0x81400000
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li t0, 0x81400000
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lw t1, 0(t0)
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lw t1, 0(t0)
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# Access fault walking page tables at megapage level
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li t0, 0xC0000000
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lw t1, 0(t0)
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# AMO operation on page table entry that causes page fault due to malformed PBMT
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# AMO operation on page table entry that causes page fault due to malformed PBMT
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li t0, 0x81200000
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li t0, 0x81200000
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jalr t0 # Attempt to fetch instruction from address causing faulty page walk
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jalr t0 # Attempt to fetch instruction from address causing faulty page walk
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@ -144,6 +152,13 @@ main:
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sfence.vma
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sfence.vma
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amoadd.w t0, t0, 0(t0)
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amoadd.w t0, t0, 0(t0)
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# point top-level page table to an illegal address and verify it faults
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li t0, 0x9000000000070000 # trap handler at non-existing memory location
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csrw satp, t0 # should cause trap
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sfence.vma
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nop
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# change back to default trap handler after checking everything that might cause an instruction page fault
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# change back to default trap handler after checking everything that might cause an instruction page fault
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jal changetodefaulthandler
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jal changetodefaulthandler
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@ -199,6 +214,9 @@ main:
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li a0, 1
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li a0, 1
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ecall
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ecall
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# wrap up
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# wrap up
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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ecall
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ecall
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@ -229,12 +247,14 @@ instructionpagefaulthandler:
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csrw mepc, ra # go back to calling function
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csrw mepc, ra # go back to calling function
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mret
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mret
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.align 4 # trap handlers must be aligned to multiple of 4
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.align 4 # trap handlers must be aligned to multiple of 16
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ipf_handler:
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ipf_handler:
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# Load trap handler stack pointer tp
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# Load trap handler stack pointer tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t1, -8(tp)
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sd t1, -8(tp)
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li t5, 0x9000000000080010
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csrw satp, t5 # make sure we are pointing to the root page table
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csrr t0, mcause # Check the cause
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csrr t0, mcause # Check the cause
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li t1, 8 # is it an ecall trap?
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li t1, 8 # is it an ecall trap?
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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@ -251,20 +271,28 @@ ipf:
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csrrw tp, mscratch, tp # restore tp
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csrrw tp, mscratch, tp # restore tp
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mret # return from trap
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mret # return from trap
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.align 4 # trap handlers must be aligned to multiple of 16
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fixsatptraphandler:
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li t5, 0x9000000000080010 # fix satp entry to normal page table root
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csrw satp, t5
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mret
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.data
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.data
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.align 16
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.align 16
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# root Page table situated at 0x80010000
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# root Page table situated at 0x80010000
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pagetable:
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pagetable:
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.8byte 0x200044C1 # 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid
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.8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid
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.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
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.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
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.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
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.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
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.8byte 0x40000000200044C1 # Bad PBMT at VA 0x180_0000000
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# next page table at 0x80011000
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# next page table at 0x80011000
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.align 12
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.align 12
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.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
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.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
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.8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
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.8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
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.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
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.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
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.8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault
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# Next page table at 0x80012000 for gigapage at 0x80000000
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# Next page table at 0x80012000 for gigapage at 0x80000000
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