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186 lines
10 KiB
Systemverilog
186 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// cacheway
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 7 July 2021
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// Modified: 20 January 2023
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cacheway import cvw::*; #(parameter cvw_t P,
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parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
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input logic [$clog2(NUMLINES)-1:0] CacheSetData, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
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input logic [$clog2(NUMLINES)-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
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input logic [PA_BITS-1:0] PAdr, // Physical address
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input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only)
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input logic SetValid, // Set the valid bit in the selected way and set
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input logic ClearValid, // Clear the valid bit in the selected way and set
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input logic SetDirty, // Set the dirty bit in the selected way and set
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input logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
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input logic ClearDirty, // Clear the dirty bit in the selected way and set
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input logic FlushCache, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
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input logic VictimWay, // LRU selected this way as victim to evict
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input logic FlushWay, // This way is selected for flush and possible writeback if dirty
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input logic InvalidateCache,// Clear all valid bits
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input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
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output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
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output logic HitWay, // This way hits
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output logic ValidWay, // This way is valid
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output logic HitDirtyWay, // The hit way is dirty
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output logic DirtyWay , // The selected way is dirty
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output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
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localparam WORDSPERLINE = LINELEN/XLEN;
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localparam BYTESPERLINE = LINELEN/8;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(XLEN/8);
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localparam BYTESPERWORD = XLEN/8;
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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logic [TAGLEN-1:0] ReadTag;
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logic Dirty;
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logic SelDirty;
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logic SelectedWriteWordEn;
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logic [LINELEN/8-1:0] FinalByteMask;
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logic SetValidEN, ClearValidEN;
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logic SetValidWay;
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logic ClearValidWay;
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logic SetDirtyWay;
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logic ClearDirtyWay;
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logic SelNonHit;
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logic SelData;
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logic InvalidateCacheDelay;
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if (!READ_ONLY_CACHE) begin:flushlogic
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logic FlushWayEn;
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mux2 #(1) seltagmux(VictimWay, FlushWay, FlushCache, SelDirty);
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// FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
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// coverage off -item e 1 -fecexprrow 3
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// nonzero ways will never see FlushCache=0 while FlushWay=1 since FlushWay only advances on a subset of FlushCache assertion cases.
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assign FlushWayEn = FlushWay & FlushCache;
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assign SelNonHit = FlushWayEn | SelWay;
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end else begin:flushlogic // no flush operation for read-only caches.
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assign SelDirty = VictimWay;
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assign SelNonHit = SelWay;
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end
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mux2 #(1) selectedwaymux(HitWay, SelDirty, SelNonHit , SelData);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Enable demux
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/////////////////////////////////////////////////////////////////////////////////////////////
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assign SetValidWay = SetValid & SelData;
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assign ClearValidWay = ClearValid & SelData; // exclusion-tag: icache ClearValidWay
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assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
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assign ClearDirtyWay = ClearDirty & SelData;
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
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assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
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assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache ClearValidEN
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// If writing the whole line set all write enables to 1, else only set the correct word.
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assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
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.addr(CacheSetTag), .dout(ReadTag),
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.din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
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// AND portion of distributed tag multiplexer
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assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
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assign HitDirtyWay = Dirty & ValidWay;
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assign DirtyWay = SelDirty & HitDirtyWay; // exclusion-tag: icache DirtyWay
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; // exclusion-tag: dcache HitWay
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flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Data Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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genvar words;
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localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
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localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
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localparam LOGNUMSRAM = $clog2(NUMSRAM);
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for(words = 0; words < NUMSRAM; words++) begin: word
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if (!READ_ONLY_CACHE) begin:wordram
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ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
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.dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end else begin:wordram // no byte-enable needed for i$.
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ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
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.dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
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.we(SelectedWriteWordEn));
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end
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end
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// AND portion of distributed read multiplexers
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assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Valid Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset) ValidBits <= #1 '0;
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if(CacheEn) begin
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ValidWay <= #1 ValidBits[CacheSetTag];
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if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
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else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay;
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else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; // exclusion-tag: icache ClearValidBits
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end
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty bits
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if (!READ_ONLY_CACHE) begin:dirty
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always_ff @(posedge clk) begin
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// reset is optional. Consider merging with TAG array in the future.
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//if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if(CacheEn) begin
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Dirty <= #1 DirtyBits[CacheSetTag];
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if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; // exclusion-tag: cache UpdateDirty
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end
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end
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end else assign Dirty = 1'b0;
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endmodule
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