Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/openhwgroup/cvw into Z_enable

Browse Source
This commit is contained in:
Daniyal-R-A 2024-11-07 01:52:47 -08:00
commit de703b355d
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bin/wsim
View File

@ -90,9 +90,10 @@ else: EnableLog = 0
prefix = ""
if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
if (args.sim == "questa" or args.sim == "vcs"):
prefix = "IMPERAS_TOOLS=" + os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(prefix): # If config is a derivative, look for imperas.ic in derivative configs
prefix = "IMPERAS_TOOLS=" + os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
prefix = "IMPERAS_TOOLS=" + imperasicPath
# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
if (args.sim == "questa"):
prefix = "MTI_VCO_MODE=64 " + prefix

4
src/fpu/fctrl.sv
View File

@ -248,9 +248,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
// coverage off
// Not covered in testing because rv64gc is not RV64Q or RV32D
7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.d.x (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_1_0; // fmvp.d.x (Zfa)
7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.q.x (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_1_0; // fmvp.q.x (Zfa)
// coverage on
endcase
endcase