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Renamed DivBusy to FDivBusyE in FPU

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This commit is contained in:
David Harris 2022-11-16 10:13:27 -08:00
parent e008d663f4
commit ddba68605e
4 changed files with 13 additions and 15 deletions
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6
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -48,7 +48,7 @@ module fdivsqrt(
input logic [2:0] Funct3E, Funct3M, input logic [2:0] Funct3E, Funct3M,
input logic MDUE, W64E, input logic MDUE, W64E,
output logic DivSM, output logic DivSM,
output logic DivBusy, output logic FDivBusyE,
output logic DivDone, output logic DivDone,
output logic [`NE+1:0] QeM, output logic [`NE+1:0] QeM,
output logic [`DIVb:0] QmM output logic [`DIVb:0] QmM
@ -75,14 +75,14 @@ module fdivsqrt(
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE, .clk, .reset, .FmtE, .XsE, .SqrtE,
.DivBusy, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .FDivBusyE, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .MDUE, .n, .XNaNE, .YNaNE, .MDUE, .n,
.XInfE, .YInfE, .WZero, .SpecialCaseM); .XInfE, .YInfE, .WZero, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter( fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
.DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap, .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap,
.DivBusy); .FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc( fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),

8
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -47,7 +47,7 @@ module fdivsqrtfsm(
input logic [`DIVBLEN:0] n, input logic [`DIVBLEN:0] n,
output logic DivStartE, output logic DivStartE,
output logic DivDone, output logic DivDone,
output logic DivBusy, output logic FDivBusyE,
output logic SpecialCaseM output logic SpecialCaseM
); );
@ -60,13 +60,11 @@ module fdivsqrtfsm(
// *** start logic is presently in fctl. Make it look more like integer division start logic // *** start logic is presently in fctl. Make it look more like integer division start logic
// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division // DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
assign DivStartE = (FDivStartE | IDivStartE); // & (state == IDLE) & ~StallM; assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
//assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
assign DivDone = (state == DONE) | (WZero & (state == BUSY)); assign DivDone = (state == DONE) | (WZero & (state == BUSY));
assign DivBusy = (state == BUSY & ~DivDone); assign FDivBusyE = (state == BUSY & ~DivDone);
// Divider control signals from MDU // Divider control signals from MDU
//assign DivStartE = DivE & (state == IDLE) & ~StallM;
//assign DivBusyE = (state == BUSY) | DivStartE; //assign DivBusyE = (state == BUSY) | DivStartE;
// terminate immediately on special cases // terminate immediately on special cases

12
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -33,7 +33,7 @@
module fdivsqrtiter( module fdivsqrtiter(
input logic clk, input logic clk,
input logic DivStartE, input logic DivStartE,
input logic DivBusy, input logic FDivBusyE,
input logic [`NE-1:0] Xe, Ye, input logic [`NE-1:0] Xe, Ye,
input logic XZeroE, YZeroE, input logic XZeroE, YZeroE,
input logic SqrtE, input logic SqrtE,
@ -85,8 +85,8 @@ module fdivsqrtiter(
// Residual WS/SC registers/initializaiton mux // Residual WS/SC registers/initializaiton mux
mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN); mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN);
mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, DivStartE, WCN); mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, DivStartE, WCN);
flopen #(`DIVb+4) wsflop(clk, DivStartE|DivBusy, WSN, WS[0]); flopen #(`DIVb+4) wsflop(clk, DivStartE|FDivBusyE, WSN, WS[0]);
flopen #(`DIVb+4) wcflop(clk, DivStartE|DivBusy, WCN, WC[0]); flopen #(`DIVb+4) wcflop(clk, DivStartE|FDivBusyE, WCN, WC[0]);
// UOTFC Result U and UM registers/initialization mux // UOTFC Result U and UM registers/initialization mux
// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division
@ -94,8 +94,8 @@ module fdivsqrtiter(
assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}}; assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux); mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux); mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux);
flopen #(`DIVb+1) UReg(clk, DivStartE|DivBusy, UMux, U[0]); flopen #(`DIVb+1) UReg(clk, DivStartE|FDivBusyE, UMux, U[0]);
flopen #(`DIVb+1) UMReg(clk, DivStartE|DivBusy, UMMux, UM[0]); flopen #(`DIVb+1) UMReg(clk, DivStartE|FDivBusyE, UMMux, UM[0]);
// C register/initialization mux // C register/initialization mux
// Initialize C to -1 for sqrt and -R for division // Initialize C to -1 for sqrt and -R for division
@ -103,7 +103,7 @@ module fdivsqrtiter(
assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10; assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
assign initC = {initCUpper, {`DIVb{1'b0}}}; assign initC = {initCUpper, {`DIVb{1'b0}}};
mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStartE, CMux); mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStartE, CMux);
flopen #(`DIVb+2) cflop(clk, DivStartE|DivBusy, CMux, C[0]); flopen #(`DIVb+2) cflop(clk, DivStartE|FDivBusyE, CMux, C[0]);
// Divisior register // Divisior register
flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D); flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D);

2
pipelined/src/fpu/fpu.sv
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@ -263,7 +263,7 @@ module fpu (
fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
.StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal .StallE, .StallM, .DivSM, .FDivBusyE, .QeM,
.QmM, .DivDone(DivDoneM)); .QmM, .DivDone(DivDoneM));
// //